26a526c256
The newly added code causes a build failure when -Werror is set:
drivers/soc/qcom/spm.c:388:12: error: 'spm_get_cpu' defined but not used [-Werror=unused-function]
Remove the #ifdef and instead use an IS_ENABLED() check that lets the
compiler perform dead code elimination instead of the preprocessor.
Fixes: 6496dba142
("soc: qcom: spm: add support for voltage regulator")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20240221154457.2007420-1-arnd@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
576 lines
16 KiB
C
576 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
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* Copyright (c) 2014,2015, Linaro Ltd.
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*
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* SAW power controller driver
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*/
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#include <linux/bitfield.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/linear_range.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/smp.h>
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#include <linux/regulator/driver.h>
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#include <soc/qcom/spm.h>
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#define FIELD_SET(current, mask, val) \
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(((current) & ~(mask)) | FIELD_PREP((mask), (val)))
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#define SPM_CTL_INDEX 0x7f
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#define SPM_CTL_INDEX_SHIFT 4
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#define SPM_CTL_EN BIT(0)
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/* These registers might be specific to SPM 1.1 */
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#define SPM_VCTL_VLVL GENMASK(7, 0)
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#define SPM_PMIC_DATA_0_VLVL GENMASK(7, 0)
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#define SPM_PMIC_DATA_1_MIN_VSEL GENMASK(5, 0)
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#define SPM_PMIC_DATA_1_MAX_VSEL GENMASK(21, 16)
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#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27)
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#define SPM_AVS_CTL_MAX_VLVL GENMASK(22, 17)
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#define SPM_AVS_CTL_MIN_VLVL GENMASK(15, 10)
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enum spm_reg {
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SPM_REG_CFG,
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SPM_REG_SPM_CTL,
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SPM_REG_DLY,
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SPM_REG_PMIC_DLY,
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SPM_REG_PMIC_DATA_0,
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SPM_REG_PMIC_DATA_1,
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SPM_REG_VCTL,
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SPM_REG_SEQ_ENTRY,
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SPM_REG_STS0,
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SPM_REG_STS1,
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SPM_REG_PMIC_STS,
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SPM_REG_AVS_CTL,
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SPM_REG_AVS_LIMIT,
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SPM_REG_RST,
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SPM_REG_NR,
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};
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#define MAX_PMIC_DATA 2
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#define MAX_SEQ_DATA 64
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struct spm_reg_data {
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const u16 *reg_offset;
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u32 spm_cfg;
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u32 spm_dly;
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u32 pmic_dly;
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u32 pmic_data[MAX_PMIC_DATA];
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u32 avs_ctl;
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u32 avs_limit;
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u8 seq[MAX_SEQ_DATA];
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u8 start_index[PM_SLEEP_MODE_NR];
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smp_call_func_t set_vdd;
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/* for now we support only a single range */
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struct linear_range *range;
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unsigned int ramp_delay;
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unsigned int init_uV;
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};
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struct spm_driver_data {
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void __iomem *reg_base;
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const struct spm_reg_data *reg_data;
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struct device *dev;
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unsigned int volt_sel;
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int reg_cpu;
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};
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static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = {
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[SPM_REG_AVS_CTL] = 0x904,
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[SPM_REG_AVS_LIMIT] = 0x908,
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};
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static const struct spm_reg_data spm_reg_660_gold_l2 = {
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.reg_offset = spm_reg_offset_v4_1,
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.avs_ctl = 0x1010031,
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.avs_limit = 0x4580458,
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};
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static const struct spm_reg_data spm_reg_660_silver_l2 = {
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.reg_offset = spm_reg_offset_v4_1,
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.avs_ctl = 0x101c031,
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.avs_limit = 0x4580458,
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};
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static const struct spm_reg_data spm_reg_8998_gold_l2 = {
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.reg_offset = spm_reg_offset_v4_1,
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.avs_ctl = 0x1010031,
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.avs_limit = 0x4700470,
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};
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static const struct spm_reg_data spm_reg_8998_silver_l2 = {
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.reg_offset = spm_reg_offset_v4_1,
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.avs_ctl = 0x1010031,
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.avs_limit = 0x4200420,
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};
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static const u16 spm_reg_offset_v3_0[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x30,
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[SPM_REG_DLY] = 0x34,
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[SPM_REG_SEQ_ENTRY] = 0x400,
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};
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/* SPM register data for 8909 */
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static const struct spm_reg_data spm_reg_8909_cpu = {
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.reg_offset = spm_reg_offset_v3_0,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
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0x5B, 0x60, 0x03, 0x60, 0x76, 0x76, 0x0B, 0x94, 0x5B, 0x80,
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0x10, 0x26, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 5,
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};
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/* SPM register data for 8916 */
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static const struct spm_reg_data spm_reg_8916_cpu = {
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.reg_offset = spm_reg_offset_v3_0,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
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0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
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0x80, 0x10, 0x26, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 5,
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};
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static const struct spm_reg_data spm_reg_8939_cpu = {
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.reg_offset = spm_reg_offset_v3_0,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x50, 0x1B, 0x10, 0x80,
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0x30, 0x90, 0x5B, 0x60, 0x50, 0x03, 0x60, 0x76, 0x76, 0x0B,
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0x50, 0x1B, 0x94, 0x5B, 0x80, 0x10, 0x26, 0x30, 0x50, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 5,
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};
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static const u16 spm_reg_offset_v2_3[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x30,
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[SPM_REG_DLY] = 0x34,
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[SPM_REG_PMIC_DATA_0] = 0x40,
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[SPM_REG_PMIC_DATA_1] = 0x44,
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};
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/* SPM register data for 8976 */
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static const struct spm_reg_data spm_reg_8976_gold_l2 = {
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.reg_offset = spm_reg_offset_v2_3,
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.spm_cfg = 0x14,
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.spm_dly = 0x3c11840a,
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.pmic_data[0] = 0x03030080,
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.pmic_data[1] = 0x00030000,
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 3,
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};
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static const struct spm_reg_data spm_reg_8976_silver_l2 = {
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.reg_offset = spm_reg_offset_v2_3,
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.spm_cfg = 0x14,
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.spm_dly = 0x3c102800,
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.pmic_data[0] = 0x03030080,
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.pmic_data[1] = 0x00030000,
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 2,
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};
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static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_SPM_CTL] = 0x30,
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[SPM_REG_DLY] = 0x34,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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/* SPM register data for 8974, 8084 */
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static const struct spm_reg_data spm_reg_8974_8084_cpu = {
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.reg_offset = spm_reg_offset_v2_1,
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.spm_cfg = 0x1,
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.spm_dly = 0x3C102800,
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.seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
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0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
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0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 3,
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};
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/* SPM register data for 8226 */
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static const struct spm_reg_data spm_reg_8226_cpu = {
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.reg_offset = spm_reg_offset_v2_1,
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.spm_cfg = 0x0,
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.spm_dly = 0x3C102800,
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.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
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0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
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0x80, 0x10, 0x26, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 5,
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};
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static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
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[SPM_REG_CFG] = 0x08,
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[SPM_REG_STS0] = 0x0c,
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[SPM_REG_STS1] = 0x10,
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[SPM_REG_VCTL] = 0x14,
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[SPM_REG_AVS_CTL] = 0x18,
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[SPM_REG_SPM_CTL] = 0x20,
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[SPM_REG_PMIC_DLY] = 0x24,
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[SPM_REG_PMIC_DATA_0] = 0x28,
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[SPM_REG_PMIC_DATA_1] = 0x2C,
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[SPM_REG_SEQ_ENTRY] = 0x80,
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};
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static void smp_set_vdd_v1_1(void *data);
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/* SPM register data for 8064 */
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static struct linear_range spm_v1_1_regulator_range =
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REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500);
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static const struct spm_reg_data spm_reg_8064_cpu = {
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.reg_offset = spm_reg_offset_v1_1,
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.spm_cfg = 0x1F,
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.pmic_dly = 0x02020004,
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.pmic_data[0] = 0x0084009C,
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.pmic_data[1] = 0x00A4001C,
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.seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
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0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
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.start_index[PM_SLEEP_MODE_STBY] = 0,
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.start_index[PM_SLEEP_MODE_SPC] = 2,
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.set_vdd = smp_set_vdd_v1_1,
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.range = &spm_v1_1_regulator_range,
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.init_uV = 1300000,
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.ramp_delay = 1250,
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};
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static inline void spm_register_write(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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if (drv->reg_data->reg_offset[reg])
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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}
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/* Ensure a guaranteed write, before return */
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static inline void spm_register_write_sync(struct spm_driver_data *drv,
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enum spm_reg reg, u32 val)
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{
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u32 ret;
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if (!drv->reg_data->reg_offset[reg])
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return;
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do {
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writel_relaxed(val, drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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ret = readl_relaxed(drv->reg_base +
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drv->reg_data->reg_offset[reg]);
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if (ret == val)
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break;
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cpu_relax();
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} while (1);
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}
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static inline u32 spm_register_read(struct spm_driver_data *drv,
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enum spm_reg reg)
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{
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return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
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}
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void spm_set_low_power_mode(struct spm_driver_data *drv,
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enum pm_sleep_mode mode)
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{
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u32 start_index;
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u32 ctl_val;
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start_index = drv->reg_data->start_index[mode];
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ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
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ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
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ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
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ctl_val |= SPM_CTL_EN;
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spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
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}
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static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector)
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{
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struct spm_driver_data *drv = rdev_get_drvdata(rdev);
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drv->volt_sel = selector;
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/* Always do the SAW register writes on the corresponding CPU */
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return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
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}
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static int spm_get_voltage_sel(struct regulator_dev *rdev)
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{
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struct spm_driver_data *drv = rdev_get_drvdata(rdev);
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return drv->volt_sel;
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}
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static const struct regulator_ops spm_reg_ops = {
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.set_voltage_sel = spm_set_voltage_sel,
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.get_voltage_sel = spm_get_voltage_sel,
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.list_voltage = regulator_list_voltage_linear_range,
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.set_voltage_time_sel = regulator_set_voltage_time_sel,
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};
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static void smp_set_vdd_v1_1(void *data)
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{
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struct spm_driver_data *drv = data;
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unsigned int vctl, data0, data1, avs_ctl, sts;
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unsigned int vlevel, volt_sel;
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bool avs_enabled;
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volt_sel = drv->volt_sel;
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vlevel = volt_sel | 0x80; /* band */
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avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL);
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vctl = spm_register_read(drv, SPM_REG_VCTL);
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data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0);
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data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1);
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avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED;
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/* If AVS is enabled, switch it off during the voltage change */
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if (avs_enabled) {
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avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED;
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spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
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}
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/* Kick the state machine back to idle */
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spm_register_write(drv, SPM_REG_RST, 1);
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vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel);
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data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel);
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data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MIN_VSEL, volt_sel);
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data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MAX_VSEL, volt_sel);
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spm_register_write(drv, SPM_REG_VCTL, vctl);
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spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0);
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spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1);
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if (read_poll_timeout_atomic(spm_register_read,
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sts, sts == vlevel,
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1, 200, false,
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drv, SPM_REG_STS1)) {
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dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel);
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goto enable_avs;
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}
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if (avs_enabled) {
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unsigned int max_avs = volt_sel;
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unsigned int min_avs = max(max_avs, 4U) - 4;
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avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs);
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avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs);
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spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
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}
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enable_avs:
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if (avs_enabled) {
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avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED;
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spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
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}
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}
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static int spm_get_cpu(struct device *dev)
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{
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int cpu;
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bool found;
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for_each_possible_cpu(cpu) {
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struct device_node *cpu_node, *saw_node;
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cpu_node = of_cpu_device_node_get(cpu);
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if (!cpu_node)
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continue;
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saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
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found = (saw_node == dev->of_node);
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of_node_put(saw_node);
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of_node_put(cpu_node);
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if (found)
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return cpu;
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}
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/* L2 SPM is not bound to any CPU, voltage setting is not supported */
|
|
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
|
|
{
|
|
struct regulator_config config = {
|
|
.dev = dev,
|
|
.driver_data = drv,
|
|
};
|
|
struct regulator_desc *rdesc;
|
|
struct regulator_dev *rdev;
|
|
int ret;
|
|
bool found;
|
|
|
|
if (!drv->reg_data->set_vdd)
|
|
return 0;
|
|
|
|
rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL);
|
|
if (!rdesc)
|
|
return -ENOMEM;
|
|
|
|
rdesc->name = "spm";
|
|
rdesc->of_match = of_match_ptr("regulator");
|
|
rdesc->type = REGULATOR_VOLTAGE;
|
|
rdesc->owner = THIS_MODULE;
|
|
rdesc->ops = &spm_reg_ops;
|
|
|
|
rdesc->linear_ranges = drv->reg_data->range;
|
|
rdesc->n_linear_ranges = 1;
|
|
rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1;
|
|
rdesc->ramp_delay = drv->reg_data->ramp_delay;
|
|
|
|
ret = spm_get_cpu(dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
drv->reg_cpu = ret;
|
|
dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu);
|
|
|
|
/*
|
|
* Program initial voltage, otherwise registration will also try
|
|
* setting the voltage, which might result in undervolting the CPU.
|
|
*/
|
|
drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV,
|
|
rdesc->uV_step);
|
|
ret = linear_range_get_selector_high(drv->reg_data->range,
|
|
drv->reg_data->init_uV,
|
|
&drv->volt_sel,
|
|
&found);
|
|
if (ret) {
|
|
dev_err(dev, "Initial uV value out of bounds\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Always do the SAW register writes on the corresponding CPU */
|
|
smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
|
|
|
|
rdev = devm_regulator_register(dev, rdesc, &config);
|
|
if (IS_ERR(rdev)) {
|
|
dev_err(dev, "failed to register regulator\n");
|
|
return PTR_ERR(rdev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id spm_match_table[] = {
|
|
{ .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
|
|
.data = &spm_reg_660_gold_l2 },
|
|
{ .compatible = "qcom,sdm660-silver-saw2-v4.1-l2",
|
|
.data = &spm_reg_660_silver_l2 },
|
|
{ .compatible = "qcom,msm8226-saw2-v2.1-cpu",
|
|
.data = &spm_reg_8226_cpu },
|
|
{ .compatible = "qcom,msm8909-saw2-v3.0-cpu",
|
|
.data = &spm_reg_8909_cpu },
|
|
{ .compatible = "qcom,msm8916-saw2-v3.0-cpu",
|
|
.data = &spm_reg_8916_cpu },
|
|
{ .compatible = "qcom,msm8939-saw2-v3.0-cpu",
|
|
.data = &spm_reg_8939_cpu },
|
|
{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
|
|
.data = &spm_reg_8974_8084_cpu },
|
|
{ .compatible = "qcom,msm8976-gold-saw2-v2.3-l2",
|
|
.data = &spm_reg_8976_gold_l2 },
|
|
{ .compatible = "qcom,msm8976-silver-saw2-v2.3-l2",
|
|
.data = &spm_reg_8976_silver_l2 },
|
|
{ .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
|
|
.data = &spm_reg_8998_gold_l2 },
|
|
{ .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",
|
|
.data = &spm_reg_8998_silver_l2 },
|
|
{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
|
|
.data = &spm_reg_8974_8084_cpu },
|
|
{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
|
|
.data = &spm_reg_8064_cpu },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, spm_match_table);
|
|
|
|
static int spm_dev_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *match_id;
|
|
struct spm_driver_data *drv;
|
|
void __iomem *addr;
|
|
|
|
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
|
|
if (!drv)
|
|
return -ENOMEM;
|
|
|
|
drv->reg_base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(drv->reg_base))
|
|
return PTR_ERR(drv->reg_base);
|
|
|
|
match_id = of_match_node(spm_match_table, pdev->dev.of_node);
|
|
if (!match_id)
|
|
return -ENODEV;
|
|
|
|
drv->reg_data = match_id->data;
|
|
drv->dev = &pdev->dev;
|
|
platform_set_drvdata(pdev, drv);
|
|
|
|
/* Write the SPM sequences first.. */
|
|
addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
|
|
__iowrite32_copy(addr, drv->reg_data->seq,
|
|
ARRAY_SIZE(drv->reg_data->seq) / 4);
|
|
|
|
/*
|
|
* ..and then the control registers.
|
|
* On some SoC if the control registers are written first and if the
|
|
* CPU was held in reset, the reset signal could trigger the SPM state
|
|
* machine, before the sequences are completely written.
|
|
*/
|
|
spm_register_write(drv, SPM_REG_AVS_CTL, drv->reg_data->avs_ctl);
|
|
spm_register_write(drv, SPM_REG_AVS_LIMIT, drv->reg_data->avs_limit);
|
|
spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
|
|
spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
|
|
spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
|
|
spm_register_write(drv, SPM_REG_PMIC_DATA_0,
|
|
drv->reg_data->pmic_data[0]);
|
|
spm_register_write(drv, SPM_REG_PMIC_DATA_1,
|
|
drv->reg_data->pmic_data[1]);
|
|
|
|
/* Set up Standby as the default low power mode */
|
|
if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
|
|
spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
|
|
|
|
if (IS_ENABLED(CONFIG_REGULATOR))
|
|
return spm_register_regulator(&pdev->dev, drv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver spm_driver = {
|
|
.probe = spm_dev_probe,
|
|
.driver = {
|
|
.name = "qcom_spm",
|
|
.of_match_table = spm_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init qcom_spm_init(void)
|
|
{
|
|
return platform_driver_register(&spm_driver);
|
|
}
|
|
arch_initcall(qcom_spm_init);
|
|
|
|
MODULE_LICENSE("GPL v2");
|