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Shaokun Zhang eb4f521325 drivers/perf: hisi: Fixup one DDRC PMU register offset

For DDRC PMU, each PMU counter is fixed-purpose. There is a mismatch
between perf list and driver definition on rw_chg event.
# perf list | grep chg
  hisi_sccl1_ddrc0/rnk_chg/                          [Kernel PMU event]
  hisi_sccl1_ddrc0/rw_chg/                           [Kernel PMU event]
But the register offset of rw_chg event is not defined in the driver,
meanwhile bnk_chg register offset is mis-defined, let's fixup it.

Fixes: 904dcf03f086 ("perf: hisi: Add support for HiSilicon SoC DDRC PMU driver")
Cc: stable@vger.kernel.org
Cc: John Garry <john.garry@huawei.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Reported-by: Weijian Huang <huangweijian4@hisilicon.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

2019-01-04 10:13:27 +00:00

hisilicon

drivers/perf: hisi: Fixup one DDRC PMU register offset

2019-01-04 10:13:27 +00:00

arm_dsu_pmu.c

perf: Fix sibling iteration

2018-03-16 20:44:12 +01:00

arm_pmu_acpi.c

arm_pmu: acpi: request IRQs up-front

2018-02-20 11:34:54 +00:00

arm_pmu_platform.c

perf: Convert to using %pOFn instead of device_node.name