2bea59d388
Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the eASIC N5X platform. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210212143059.478554-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
47 lines
903 B
YAML
47 lines
903 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel SoCFPGA eASIC N5X platform clock controller binding
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maintainers:
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- Dinh Nguyen <dinguyen@kernel.org>
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description:
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The Intel eASIC N5X Clock controller is an integrated clock controller, which
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generates and supplies to all modules.
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properties:
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compatible:
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const: intel,easic-n5x-clkmgr
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'#clock-cells':
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const: 1
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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# Clock controller node:
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- |
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clkmgr: clock-controller@ffd10000 {
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compatible = "intel,easic-n5x-clkmgr";
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reg = <0xffd10000 0x1000>;
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clocks = <&osc1>;
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#clock-cells = <1>;
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};
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...
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