2145e77fec
The new PEBS Record Format 5 is similar to the PEBS Record Format 4. The only difference is the layout of the Counter Reset fields of the PEBS Config Buffer in the DS area. For the PEBS format 4, the Counter Reset fields allocation is for 8 general-purpose counters followed by 4 fixed-function counters. For the PEBS format 5, the Counter Reset fields allocation is for 32 general-purpose counters followed by 16 fixed-function counters. Extend the MAX_PEBS_EVENTS to 32. Add MAX_PEBS_EVENTS_FMT4 for the previous platform. Except for the DS auto-reload code, other places already assume 32 counters. Only check the PEBS_FMT in the DS auto-reload code. Extend the MAX_FIXED_PEBS_EVENTS to 16, which only impacts the size of struct debug_store and some local temporary variables. The size of struct debug_store increases 288B, which is small and should be acceptable. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/1643750603-100733-1-git-send-email-kan.liang@linux.intel.com
39 lines
882 B
C
39 lines
882 B
C
#ifndef _ASM_INTEL_DS_H
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#define _ASM_INTEL_DS_H
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#include <linux/percpu-defs.h>
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#define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
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#define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
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/* The maximal number of PEBS events: */
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#define MAX_PEBS_EVENTS_FMT4 8
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#define MAX_PEBS_EVENTS 32
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#define MAX_FIXED_PEBS_EVENTS 16
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/*
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* A debug store configuration.
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*
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* We only support architectures that use 64bit fields.
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*/
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struct debug_store {
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u64 bts_buffer_base;
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u64 bts_index;
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u64 bts_absolute_maximum;
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u64 bts_interrupt_threshold;
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u64 pebs_buffer_base;
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u64 pebs_index;
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u64 pebs_absolute_maximum;
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u64 pebs_interrupt_threshold;
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u64 pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS];
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} __aligned(PAGE_SIZE);
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DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
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struct debug_store_buffers {
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char bts_buffer[BTS_BUFFER_SIZE];
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char pebs_buffer[PEBS_BUFFER_SIZE];
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};
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#endif
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