e2fd06f6be
mach-imx directly references to the irq field in struct irq_data, and uses this to directly poke hardware register. But irq is the *virtual* irq number, something that has nothing to do with the actual HW irq (stored in the hwirq field). And once we put the stacked domain code in action, the whole thing explodes, as these two values are *very* different. Just replacing all instances of irq with hwirq fixes the issue. Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
142 lines
3.1 KiB
C
142 lines
3.1 KiB
C
/*
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* Copyright 2011-2013 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include "common.h"
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#define GPC_IMR1 0x008
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#define GPC_PGC_CPU_PDN 0x2a0
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#define IMR_NUM 4
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static void __iomem *gpc_base;
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static u32 gpc_wake_irqs[IMR_NUM];
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static u32 gpc_saved_imrs[IMR_NUM];
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void imx_gpc_pre_suspend(bool arm_power_off)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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/* Tell GPC to power off ARM core when suspend */
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if (arm_power_off)
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writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
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for (i = 0; i < IMR_NUM; i++) {
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gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
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writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
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}
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}
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void imx_gpc_post_resume(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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/* Keep ARM core powered on for other low-power modes */
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writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
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}
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static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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unsigned int idx = d->hwirq / 32 - 1;
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u32 mask;
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/* Sanity check for SPI irq */
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if (d->hwirq < 32)
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return -EINVAL;
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mask = 1 << d->hwirq % 32;
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gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
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gpc_wake_irqs[idx] & ~mask;
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return 0;
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}
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void imx_gpc_mask_all(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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for (i = 0; i < IMR_NUM; i++) {
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gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
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writel_relaxed(~0, reg_imr1 + i * 4);
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}
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}
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void imx_gpc_restore_all(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
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}
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void imx_gpc_irq_unmask(struct irq_data *d)
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{
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void __iomem *reg;
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u32 val;
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/* Sanity check for SPI irq */
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if (d->hwirq < 32)
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return;
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reg = gpc_base + GPC_IMR1 + (d->hwirq / 32 - 1) * 4;
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val = readl_relaxed(reg);
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val &= ~(1 << d->hwirq % 32);
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writel_relaxed(val, reg);
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}
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void imx_gpc_irq_mask(struct irq_data *d)
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{
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void __iomem *reg;
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u32 val;
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/* Sanity check for SPI irq */
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if (d->hwirq < 32)
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return;
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reg = gpc_base + GPC_IMR1 + (d->hwirq / 32 - 1) * 4;
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val = readl_relaxed(reg);
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val |= 1 << (d->hwirq % 32);
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writel_relaxed(val, reg);
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}
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void __init imx_gpc_init(void)
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{
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struct device_node *np;
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int i;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
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gpc_base = of_iomap(np, 0);
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WARN_ON(!gpc_base);
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/* Initially mask all interrupts */
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
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/* Register GPC as the secondary interrupt controller behind GIC */
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gic_arch_extn.irq_mask = imx_gpc_irq_mask;
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gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
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gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
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}
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