Jisheng Zhang 2bf847db0c
riscv: extable: add type and data fields
This is a riscv port of commit d6e2cc564775 ("arm64: extable: add `type`
and `data` fields").

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-01-05 17:52:54 -08:00
..
2021-10-28 01:02:44 +02:00
2020-03-05 16:13:47 +01:00