befe87380e
Add the missing MODULE_DESCRIPTION() in the Amlogic clock modules missing it. Reported-by: Jeff Johnson <quic_jjohnson@quicinc.com> Closes: https://lore.kernel.org/linux-clk/964210f1-671f-4ecc-bdb7-3cf53089c327@quicinc.com Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240611133512.341817-1-jbrunet@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
748 lines
17 KiB
C
748 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Amlogic C3 PLL Controller Driver
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*
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* Copyright (c) 2023 Amlogic, inc.
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* Author: Chuan Liu <chuan.liu@amlogic.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-regmap.h"
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#include "clk-pll.h"
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#include "meson-clkc-utils.h"
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#include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
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#define ANACTRL_FIXPLL_CTRL4 0x50
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#define ANACTRL_GP0PLL_CTRL0 0x80
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#define ANACTRL_GP0PLL_CTRL1 0x84
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#define ANACTRL_GP0PLL_CTRL2 0x88
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#define ANACTRL_GP0PLL_CTRL3 0x8c
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#define ANACTRL_GP0PLL_CTRL4 0x90
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#define ANACTRL_GP0PLL_CTRL5 0x94
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#define ANACTRL_GP0PLL_CTRL6 0x98
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#define ANACTRL_HIFIPLL_CTRL0 0x100
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#define ANACTRL_HIFIPLL_CTRL1 0x104
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#define ANACTRL_HIFIPLL_CTRL2 0x108
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#define ANACTRL_HIFIPLL_CTRL3 0x10c
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#define ANACTRL_HIFIPLL_CTRL4 0x110
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#define ANACTRL_HIFIPLL_CTRL5 0x114
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#define ANACTRL_HIFIPLL_CTRL6 0x118
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#define ANACTRL_MPLL_CTRL0 0x180
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#define ANACTRL_MPLL_CTRL1 0x184
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#define ANACTRL_MPLL_CTRL2 0x188
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#define ANACTRL_MPLL_CTRL3 0x18c
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#define ANACTRL_MPLL_CTRL4 0x190
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static struct clk_regmap fclk_50m_en = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = ANACTRL_FIXPLL_CTRL4,
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.bit_idx = 0,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_50m_en",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "fix"
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},
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor fclk_50m = {
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.mult = 1,
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.div = 40,
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_50m",
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.ops = &clk_fixed_factor_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&fclk_50m_en.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor fclk_div2_div = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div2_div",
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.ops = &clk_fixed_factor_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "fix"
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap fclk_div2 = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = ANACTRL_FIXPLL_CTRL4,
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.bit_idx = 24,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div2",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&fclk_div2_div.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor fclk_div2p5_div = {
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.mult = 2,
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.div = 5,
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div2p5_div",
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.ops = &clk_fixed_factor_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "fix"
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap fclk_div2p5 = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = ANACTRL_FIXPLL_CTRL4,
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.bit_idx = 4,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div2p5",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&fclk_div2p5_div.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor fclk_div3_div = {
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.mult = 1,
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.div = 3,
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div3_div",
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.ops = &clk_fixed_factor_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "fix"
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap fclk_div3 = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = ANACTRL_FIXPLL_CTRL4,
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.bit_idx = 20,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div3",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&fclk_div3_div.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor fclk_div4_div = {
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.mult = 1,
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.div = 4,
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div4_div",
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.ops = &clk_fixed_factor_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "fix"
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap fclk_div4 = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = ANACTRL_FIXPLL_CTRL4,
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.bit_idx = 21,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div4",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&fclk_div4_div.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor fclk_div5_div = {
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.mult = 1,
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.div = 5,
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div5_div",
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.ops = &clk_fixed_factor_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "fix"
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap fclk_div5 = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = ANACTRL_FIXPLL_CTRL4,
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.bit_idx = 22,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div5",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&fclk_div5_div.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor fclk_div7_div = {
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.mult = 1,
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.div = 7,
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div7_div",
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.ops = &clk_fixed_factor_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "fix"
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap fclk_div7 = {
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.data = &(struct clk_regmap_gate_data) {
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.offset = ANACTRL_FIXPLL_CTRL4,
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.bit_idx = 23,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "fclk_div7",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&fclk_div7_div.hw
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},
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.num_parents = 1,
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},
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};
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static const struct reg_sequence c3_gp0_init_regs[] = {
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{ .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x0 },
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{ .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
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{ .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 },
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{ .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x3927200a },
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{ .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 },
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};
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static const struct pll_mult_range c3_gp0_pll_mult_range = {
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.min = 125,
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.max = 250,
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};
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static struct clk_regmap gp0_pll_dco = {
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.data = &(struct meson_clk_pll_data) {
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.en = {
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.reg_off = ANACTRL_GP0PLL_CTRL0,
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.shift = 28,
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.width = 1,
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},
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.m = {
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.reg_off = ANACTRL_GP0PLL_CTRL0,
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.shift = 0,
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.width = 9,
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},
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.frac = {
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.reg_off = ANACTRL_GP0PLL_CTRL1,
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.shift = 0,
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.width = 19,
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},
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.n = {
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.reg_off = ANACTRL_GP0PLL_CTRL0,
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.shift = 10,
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.width = 5,
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},
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.l = {
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.reg_off = ANACTRL_GP0PLL_CTRL0,
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.shift = 31,
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.width = 1,
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},
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.rst = {
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.reg_off = ANACTRL_GP0PLL_CTRL0,
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.shift = 29,
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.width = 1,
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},
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.range = &c3_gp0_pll_mult_range,
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.init_regs = c3_gp0_init_regs,
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.init_count = ARRAY_SIZE(c3_gp0_init_regs),
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},
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.hw.init = &(struct clk_init_data) {
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.name = "gp0_pll_dco",
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.ops = &meson_clk_pll_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "top",
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},
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.num_parents = 1,
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},
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};
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/* The maximum frequency divider supports is 32, not 128(2^7) */
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static const struct clk_div_table c3_gp0_pll_od_table[] = {
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{ 0, 1 },
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{ 1, 2 },
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{ 2, 4 },
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{ 3, 8 },
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{ 4, 16 },
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{ 5, 32 },
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{ /* sentinel */ }
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};
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static struct clk_regmap gp0_pll = {
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.data = &(struct clk_regmap_div_data) {
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.offset = ANACTRL_GP0PLL_CTRL0,
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.shift = 16,
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.width = 3,
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.table = c3_gp0_pll_od_table,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "gp0_pll",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&gp0_pll_dco.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static const struct reg_sequence c3_hifi_init_regs[] = {
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{ .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x0 },
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{ .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
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{ .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
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{ .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x3927200a },
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{ .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 },
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};
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static struct clk_regmap hifi_pll_dco = {
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.data = &(struct meson_clk_pll_data) {
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.en = {
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.reg_off = ANACTRL_HIFIPLL_CTRL0,
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.shift = 28,
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.width = 1,
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},
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.m = {
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.reg_off = ANACTRL_HIFIPLL_CTRL0,
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.shift = 0,
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.width = 8,
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},
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.frac = {
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.reg_off = ANACTRL_HIFIPLL_CTRL1,
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.shift = 0,
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.width = 19,
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},
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.n = {
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.reg_off = ANACTRL_HIFIPLL_CTRL0,
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.shift = 10,
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.width = 5,
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},
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.l = {
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.reg_off = ANACTRL_HIFIPLL_CTRL0,
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.shift = 31,
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.width = 1,
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},
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.rst = {
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.reg_off = ANACTRL_HIFIPLL_CTRL0,
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.shift = 29,
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.width = 1,
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},
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.range = &c3_gp0_pll_mult_range,
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.init_regs = c3_hifi_init_regs,
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.init_count = ARRAY_SIZE(c3_hifi_init_regs),
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},
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.hw.init = &(struct clk_init_data) {
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.name = "hifi_pll_dco",
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.ops = &meson_clk_pll_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "top",
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap hifi_pll = {
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.data = &(struct clk_regmap_div_data) {
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.offset = ANACTRL_HIFIPLL_CTRL0,
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.shift = 16,
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.width = 2,
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.flags = CLK_DIVIDER_POWER_OF_TWO,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "hifi_pll",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&hifi_pll_dco.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static const struct reg_sequence c3_mclk_init_regs[] = {
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{ .reg = ANACTRL_MPLL_CTRL1, .def = 0x1420500f },
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{ .reg = ANACTRL_MPLL_CTRL2, .def = 0x00023041 },
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{ .reg = ANACTRL_MPLL_CTRL3, .def = 0x18180000 },
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{ .reg = ANACTRL_MPLL_CTRL2, .def = 0x00023001 }
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};
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static const struct pll_mult_range c3_mclk_pll_mult_range = {
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.min = 67,
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.max = 133,
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};
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static struct clk_regmap mclk_pll_dco = {
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.data = &(struct meson_clk_pll_data) {
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.en = {
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.reg_off = ANACTRL_MPLL_CTRL0,
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.shift = 28,
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.width = 1,
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},
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.m = {
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.reg_off = ANACTRL_MPLL_CTRL0,
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.shift = 0,
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.width = 8,
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},
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.n = {
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.reg_off = ANACTRL_MPLL_CTRL0,
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.shift = 16,
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.width = 5,
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},
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.l = {
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.reg_off = ANACTRL_MPLL_CTRL0,
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.shift = 31,
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.width = 1,
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},
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.rst = {
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.reg_off = ANACTRL_MPLL_CTRL0,
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.shift = 29,
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.width = 1,
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},
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.range = &c3_mclk_pll_mult_range,
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.init_regs = c3_mclk_init_regs,
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.init_count = ARRAY_SIZE(c3_mclk_init_regs),
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},
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.hw.init = &(struct clk_init_data) {
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.name = "mclk_pll_dco",
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.ops = &meson_clk_pll_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "mclk",
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},
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.num_parents = 1,
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},
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};
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static const struct clk_div_table c3_mpll_od_table[] = {
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{ 0, 1 },
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{ 1, 2 },
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{ 2, 4 },
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{ 3, 8 },
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{ 4, 16 },
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{ /* sentinel */ }
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};
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static struct clk_regmap mclk_pll_od = {
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.data = &(struct clk_regmap_div_data) {
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.offset = ANACTRL_MPLL_CTRL0,
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.shift = 12,
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.width = 3,
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.table = c3_mpll_od_table,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "mclk_pll_od",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&mclk_pll_dco.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* both value 0 and 1 gives divide the input rate by one */
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static struct clk_regmap mclk_pll = {
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.data = &(struct clk_regmap_div_data) {
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.offset = ANACTRL_MPLL_CTRL4,
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.shift = 16,
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.width = 5,
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.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "mclk_pll",
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.ops = &clk_regmap_divider_ops,
|
|
.parent_hws = (const struct clk_hw *[]) {
|
|
&mclk_pll_od.hw
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
},
|
|
};
|
|
|
|
static const struct clk_parent_data mclk_parent[] = {
|
|
{ .hw = &mclk_pll.hw },
|
|
{ .fw_name = "mclk" },
|
|
{ .hw = &fclk_50m.hw }
|
|
};
|
|
|
|
static struct clk_regmap mclk0_sel = {
|
|
.data = &(struct clk_regmap_mux_data) {
|
|
.offset = ANACTRL_MPLL_CTRL4,
|
|
.mask = 0x3,
|
|
.shift = 4,
|
|
},
|
|
.hw.init = &(struct clk_init_data) {
|
|
.name = "mclk0_sel",
|
|
.ops = &clk_regmap_mux_ops,
|
|
.parent_data = mclk_parent,
|
|
.num_parents = ARRAY_SIZE(mclk_parent),
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap mclk0_div_en = {
|
|
.data = &(struct clk_regmap_gate_data) {
|
|
.offset = ANACTRL_MPLL_CTRL4,
|
|
.bit_idx = 1,
|
|
},
|
|
.hw.init = &(struct clk_init_data) {
|
|
.name = "mclk0_div_en",
|
|
.ops = &clk_regmap_gate_ops,
|
|
.parent_hws = (const struct clk_hw *[]) {
|
|
&mclk0_sel.hw
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap mclk0_div = {
|
|
.data = &(struct clk_regmap_div_data) {
|
|
.offset = ANACTRL_MPLL_CTRL4,
|
|
.shift = 2,
|
|
.width = 1,
|
|
},
|
|
.hw.init = &(struct clk_init_data) {
|
|
.name = "mclk0_div",
|
|
.ops = &clk_regmap_divider_ops,
|
|
.parent_hws = (const struct clk_hw *[]) {
|
|
&mclk0_div_en.hw
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap mclk0 = {
|
|
.data = &(struct clk_regmap_gate_data) {
|
|
.offset = ANACTRL_MPLL_CTRL4,
|
|
.bit_idx = 0,
|
|
},
|
|
.hw.init = &(struct clk_init_data) {
|
|
.name = "mclk0",
|
|
.ops = &clk_regmap_gate_ops,
|
|
.parent_hws = (const struct clk_hw *[]) {
|
|
&mclk0_div.hw
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap mclk1_sel = {
|
|
.data = &(struct clk_regmap_mux_data) {
|
|
.offset = ANACTRL_MPLL_CTRL4,
|
|
.mask = 0x3,
|
|
.shift = 12,
|
|
},
|
|
.hw.init = &(struct clk_init_data) {
|
|
.name = "mclk1_sel",
|
|
.ops = &clk_regmap_mux_ops,
|
|
.parent_data = mclk_parent,
|
|
.num_parents = ARRAY_SIZE(mclk_parent),
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap mclk1_div_en = {
|
|
.data = &(struct clk_regmap_gate_data) {
|
|
.offset = ANACTRL_MPLL_CTRL4,
|
|
.bit_idx = 9,
|
|
},
|
|
.hw.init = &(struct clk_init_data) {
|
|
.name = "mclk1_div_en",
|
|
.ops = &clk_regmap_gate_ops,
|
|
.parent_hws = (const struct clk_hw *[]) {
|
|
&mclk1_sel.hw
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap mclk1_div = {
|
|
.data = &(struct clk_regmap_div_data) {
|
|
.offset = ANACTRL_MPLL_CTRL4,
|
|
.shift = 10,
|
|
.width = 1,
|
|
},
|
|
.hw.init = &(struct clk_init_data) {
|
|
.name = "mclk1_div",
|
|
.ops = &clk_regmap_divider_ops,
|
|
.parent_hws = (const struct clk_hw *[]) {
|
|
&mclk1_div_en.hw
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap mclk1 = {
|
|
.data = &(struct clk_regmap_gate_data) {
|
|
.offset = ANACTRL_MPLL_CTRL4,
|
|
.bit_idx = 8,
|
|
},
|
|
.hw.init = &(struct clk_init_data) {
|
|
.name = "mclk1",
|
|
.ops = &clk_regmap_gate_ops,
|
|
.parent_hws = (const struct clk_hw *[]) {
|
|
&mclk1_div.hw
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
},
|
|
};
|
|
|
|
static struct clk_hw *c3_pll_hw_clks[] = {
|
|
[CLKID_FCLK_50M_EN] = &fclk_50m_en.hw,
|
|
[CLKID_FCLK_50M] = &fclk_50m.hw,
|
|
[CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
|
|
[CLKID_FCLK_DIV2] = &fclk_div2.hw,
|
|
[CLKID_FCLK_DIV2P5_DIV] = &fclk_div2p5_div.hw,
|
|
[CLKID_FCLK_DIV2P5] = &fclk_div2p5.hw,
|
|
[CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
|
|
[CLKID_FCLK_DIV3] = &fclk_div3.hw,
|
|
[CLKID_FCLK_DIV4_DIV] = &fclk_div4_div.hw,
|
|
[CLKID_FCLK_DIV4] = &fclk_div4.hw,
|
|
[CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
|
|
[CLKID_FCLK_DIV5] = &fclk_div5.hw,
|
|
[CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
|
|
[CLKID_FCLK_DIV7] = &fclk_div7.hw,
|
|
[CLKID_GP0_PLL_DCO] = &gp0_pll_dco.hw,
|
|
[CLKID_GP0_PLL] = &gp0_pll.hw,
|
|
[CLKID_HIFI_PLL_DCO] = &hifi_pll_dco.hw,
|
|
[CLKID_HIFI_PLL] = &hifi_pll.hw,
|
|
[CLKID_MCLK_PLL_DCO] = &mclk_pll_dco.hw,
|
|
[CLKID_MCLK_PLL_OD] = &mclk_pll_od.hw,
|
|
[CLKID_MCLK_PLL] = &mclk_pll.hw,
|
|
[CLKID_MCLK0_SEL] = &mclk0_sel.hw,
|
|
[CLKID_MCLK0_SEL_EN] = &mclk0_div_en.hw,
|
|
[CLKID_MCLK0_DIV] = &mclk0_div.hw,
|
|
[CLKID_MCLK0] = &mclk0.hw,
|
|
[CLKID_MCLK1_SEL] = &mclk1_sel.hw,
|
|
[CLKID_MCLK1_SEL_EN] = &mclk1_div_en.hw,
|
|
[CLKID_MCLK1_DIV] = &mclk1_div.hw,
|
|
[CLKID_MCLK1] = &mclk1.hw
|
|
};
|
|
|
|
/* Convenience table to populate regmap in .probe */
|
|
static struct clk_regmap *const c3_pll_clk_regmaps[] = {
|
|
&fclk_50m_en,
|
|
&fclk_div2,
|
|
&fclk_div2p5,
|
|
&fclk_div3,
|
|
&fclk_div4,
|
|
&fclk_div5,
|
|
&fclk_div7,
|
|
&gp0_pll_dco,
|
|
&gp0_pll,
|
|
&hifi_pll_dco,
|
|
&hifi_pll,
|
|
&mclk_pll_dco,
|
|
&mclk_pll_od,
|
|
&mclk_pll,
|
|
&mclk0_sel,
|
|
&mclk0_div_en,
|
|
&mclk0_div,
|
|
&mclk0,
|
|
&mclk1_sel,
|
|
&mclk1_div_en,
|
|
&mclk1_div,
|
|
&mclk1,
|
|
};
|
|
|
|
static struct regmap_config clkc_regmap_config = {
|
|
.reg_bits = 32,
|
|
.val_bits = 32,
|
|
.reg_stride = 4,
|
|
.max_register = ANACTRL_MPLL_CTRL4,
|
|
};
|
|
|
|
static struct meson_clk_hw_data c3_pll_clks = {
|
|
.hws = c3_pll_hw_clks,
|
|
.num = ARRAY_SIZE(c3_pll_hw_clks),
|
|
};
|
|
|
|
static int c3_pll_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct regmap *regmap;
|
|
void __iomem *base;
|
|
int clkid, ret, i;
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
/* Populate regmap for the regmap backed clocks */
|
|
for (i = 0; i < ARRAY_SIZE(c3_pll_clk_regmaps); i++)
|
|
c3_pll_clk_regmaps[i]->map = regmap;
|
|
|
|
for (clkid = 0; clkid < c3_pll_clks.num; clkid++) {
|
|
/* array might be sparse */
|
|
if (!c3_pll_clks.hws[clkid])
|
|
continue;
|
|
|
|
ret = devm_clk_hw_register(dev, c3_pll_clks.hws[clkid]);
|
|
if (ret) {
|
|
dev_err(dev, "Clock registration failed\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
|
|
&c3_pll_clks);
|
|
}
|
|
|
|
static const struct of_device_id c3_pll_clkc_match_table[] = {
|
|
{
|
|
.compatible = "amlogic,c3-pll-clkc",
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, c3_pll_clkc_match_table);
|
|
|
|
static struct platform_driver c3_pll_driver = {
|
|
.probe = c3_pll_probe,
|
|
.driver = {
|
|
.name = "c3-pll-clkc",
|
|
.of_match_table = c3_pll_clkc_match_table,
|
|
},
|
|
};
|
|
module_platform_driver(c3_pll_driver);
|
|
|
|
MODULE_DESCRIPTION("Amlogic C3 PLL Clock Controller driver");
|
|
MODULE_AUTHOR("Chuan Liu <chuan.liu@amlogic.com>");
|
|
MODULE_LICENSE("GPL");
|