48a8748fd0
The composite interface support the offset configuration, which is used to support mux and div in different registers. Because some sprd projects, the divider has different addresses from mux for one composite clk. Signed-off-by: Zhifeng Tang <zhifeng.tang@unisoc.com> Reviewed-by: Chunyan Zhang <zhang.lyra@gmail.com> Link: https://lore.kernel.org/r/20230913115211.11512-1-zhifeng.tang@unisoc.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
82 lines
2.1 KiB
C
82 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Spreadtrum divider clock driver
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//
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// Copyright (C) 2017 Spreadtrum, Inc.
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// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
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#include <linux/clk-provider.h>
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#include "div.h"
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static long sprd_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct sprd_div *cd = hw_to_sprd_div(hw);
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return divider_round_rate(&cd->common.hw, rate, parent_rate, NULL,
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cd->div.width, 0);
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}
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unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common,
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const struct sprd_div_internal *div,
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unsigned long parent_rate)
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{
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unsigned long val;
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unsigned int reg;
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regmap_read(common->regmap, common->reg + div->offset, ®);
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val = reg >> div->shift;
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val &= (1 << div->width) - 1;
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return divider_recalc_rate(&common->hw, parent_rate, val, NULL, 0,
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div->width);
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}
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EXPORT_SYMBOL_GPL(sprd_div_helper_recalc_rate);
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static unsigned long sprd_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sprd_div *cd = hw_to_sprd_div(hw);
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return sprd_div_helper_recalc_rate(&cd->common, &cd->div, parent_rate);
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}
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int sprd_div_helper_set_rate(const struct sprd_clk_common *common,
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const struct sprd_div_internal *div,
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unsigned long rate,
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unsigned long parent_rate)
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{
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unsigned long val;
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unsigned int reg;
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val = divider_get_val(rate, parent_rate, NULL,
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div->width, 0);
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regmap_read(common->regmap, common->reg + div->offset, ®);
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reg &= ~GENMASK(div->width + div->shift - 1, div->shift);
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regmap_write(common->regmap, common->reg + div->offset,
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reg | (val << div->shift));
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return 0;
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}
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EXPORT_SYMBOL_GPL(sprd_div_helper_set_rate);
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static int sprd_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sprd_div *cd = hw_to_sprd_div(hw);
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return sprd_div_helper_set_rate(&cd->common, &cd->div,
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rate, parent_rate);
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}
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const struct clk_ops sprd_div_ops = {
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.recalc_rate = sprd_div_recalc_rate,
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.round_rate = sprd_div_round_rate,
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.set_rate = sprd_div_set_rate,
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};
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EXPORT_SYMBOL_GPL(sprd_div_ops);
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