Stephen Boyd
e51fbc55d3
Merge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and 'clk-socfpga' into clk-next ...
* clk-rockchip:
clk: rockchip: export ACLK_VCODEC for RK3036
clk: rockchip: fix rk3568 cpll clk gate bits
clk: rockchip: Optimize PLL table memory usage
* clk-amlogic:
clk: meson: g12a: Add missing NNA source clocks for g12b
clk: meson: axg-audio: improve deferral handling
clk: meson: g12a: fix gp0 and hifi ranges
clk: meson: pll: switch to determine_rate for the PLL ops
* clk-yaml:
dt-bindings: clock: gpio-mux-clock: Convert to json-schema
* clk-zynq:
clk: zynqmp: Handle divider specific read only flag
clk: zynqmp: Use firmware specific mux clock flags
clk: zynqmp: Use firmware specific divider clock flags
clk: zynqmp: Use firmware specific common clock flags
clk: zynqmp: pll: Remove some dead code
clk: zynqmp: fix compile testing without ZYNQMP_FIRMWARE
* clk-socfpga:
clk: socfpga: clk-pll: Remove unused variable 'rc'
clk: agilex/stratix10/n5x: fix how the bypass_reg is handled
clk: agilex/stratix10: add support for the 2nd bypass
clk: agilex/stratix10: fix bypass representation
clk: agilex/stratix10: remove noc_clk
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e51fbc55d3