e7b631d798
Class-based I2C probing requires detect() and address_list to be set in the I2C client driver, see checks in i2c_detect(). It's misleading to declare I2C_CLASS_HWMON support if this precondition isn't met. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Link: https://lore.kernel.org/r/75747c6a-d414-4b07-8f66-5a5cdddc3c36@gmail.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
667 lines
15 KiB
C
667 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* max31827.c - Support for Maxim Low-Power Switch
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*
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* Copyright (c) 2023 Daniel Matyas <daniel.matyas@analog.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/hwmon.h>
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#include <linux/i2c.h>
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#include <linux/mutex.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#define MAX31827_T_REG 0x0
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#define MAX31827_CONFIGURATION_REG 0x2
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#define MAX31827_TH_REG 0x4
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#define MAX31827_TL_REG 0x6
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#define MAX31827_TH_HYST_REG 0x8
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#define MAX31827_TL_HYST_REG 0xA
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#define MAX31827_CONFIGURATION_1SHOT_MASK BIT(0)
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#define MAX31827_CONFIGURATION_CNV_RATE_MASK GENMASK(3, 1)
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#define MAX31827_CONFIGURATION_TIMEOUT_MASK BIT(5)
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#define MAX31827_CONFIGURATION_RESOLUTION_MASK GENMASK(7, 6)
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#define MAX31827_CONFIGURATION_ALRM_POL_MASK BIT(8)
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#define MAX31827_CONFIGURATION_COMP_INT_MASK BIT(9)
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#define MAX31827_CONFIGURATION_FLT_Q_MASK GENMASK(11, 10)
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#define MAX31827_CONFIGURATION_U_TEMP_STAT_MASK BIT(14)
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#define MAX31827_CONFIGURATION_O_TEMP_STAT_MASK BIT(15)
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#define MAX31827_ALRM_POL_LOW 0x0
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#define MAX31827_ALRM_POL_HIGH 0x1
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#define MAX31827_FLT_Q_1 0x0
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#define MAX31827_FLT_Q_4 0x2
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#define MAX31827_8_BIT_CNV_TIME 9
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#define MAX31827_9_BIT_CNV_TIME 18
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#define MAX31827_10_BIT_CNV_TIME 35
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#define MAX31827_12_BIT_CNV_TIME 140
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#define MAX31827_16_BIT_TO_M_DGR(x) (sign_extend32(x, 15) * 1000 / 16)
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#define MAX31827_M_DGR_TO_16_BIT(x) (((x) << 4) / 1000)
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#define MAX31827_DEVICE_ENABLE(x) ((x) ? 0xA : 0x0)
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enum chips { max31827 = 1, max31828, max31829 };
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enum max31827_cnv {
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MAX31827_CNV_1_DIV_64_HZ = 1,
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MAX31827_CNV_1_DIV_32_HZ,
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MAX31827_CNV_1_DIV_16_HZ,
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MAX31827_CNV_1_DIV_4_HZ,
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MAX31827_CNV_1_HZ,
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MAX31827_CNV_4_HZ,
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MAX31827_CNV_8_HZ,
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};
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static const u16 max31827_conversions[] = {
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[MAX31827_CNV_1_DIV_64_HZ] = 64000,
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[MAX31827_CNV_1_DIV_32_HZ] = 32000,
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[MAX31827_CNV_1_DIV_16_HZ] = 16000,
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[MAX31827_CNV_1_DIV_4_HZ] = 4000,
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[MAX31827_CNV_1_HZ] = 1000,
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[MAX31827_CNV_4_HZ] = 250,
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[MAX31827_CNV_8_HZ] = 125,
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};
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enum max31827_resolution {
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MAX31827_RES_8_BIT = 0,
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MAX31827_RES_9_BIT,
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MAX31827_RES_10_BIT,
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MAX31827_RES_12_BIT,
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};
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static const u16 max31827_resolutions[] = {
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[MAX31827_RES_8_BIT] = 1000,
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[MAX31827_RES_9_BIT] = 500,
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[MAX31827_RES_10_BIT] = 250,
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[MAX31827_RES_12_BIT] = 62,
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};
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static const u16 max31827_conv_times[] = {
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[MAX31827_RES_8_BIT] = MAX31827_8_BIT_CNV_TIME,
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[MAX31827_RES_9_BIT] = MAX31827_9_BIT_CNV_TIME,
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[MAX31827_RES_10_BIT] = MAX31827_10_BIT_CNV_TIME,
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[MAX31827_RES_12_BIT] = MAX31827_12_BIT_CNV_TIME,
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};
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struct max31827_state {
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/*
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* Prevent simultaneous access to the i2c client.
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*/
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struct mutex lock;
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struct regmap *regmap;
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bool enable;
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unsigned int resolution;
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unsigned int update_interval;
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};
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static const struct regmap_config max31827_regmap = {
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.reg_bits = 8,
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.val_bits = 16,
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.max_register = 0xA,
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};
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static int shutdown_write(struct max31827_state *st, unsigned int reg,
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unsigned int mask, unsigned int val)
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{
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unsigned int cfg;
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unsigned int cnv_rate;
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int ret;
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/*
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* Before the Temperature Threshold Alarm, Alarm Hysteresis Threshold
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* and Resolution bits from Configuration register are changed over I2C,
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* the part must be in shutdown mode.
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*
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* Mutex is used to ensure, that some other process doesn't change the
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* configuration register.
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*/
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mutex_lock(&st->lock);
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if (!st->enable) {
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if (!mask)
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ret = regmap_write(st->regmap, reg, val);
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else
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ret = regmap_update_bits(st->regmap, reg, mask, val);
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goto unlock;
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}
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ret = regmap_read(st->regmap, MAX31827_CONFIGURATION_REG, &cfg);
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if (ret)
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goto unlock;
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cnv_rate = MAX31827_CONFIGURATION_CNV_RATE_MASK & cfg;
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cfg = cfg & ~(MAX31827_CONFIGURATION_1SHOT_MASK |
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MAX31827_CONFIGURATION_CNV_RATE_MASK);
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ret = regmap_write(st->regmap, MAX31827_CONFIGURATION_REG, cfg);
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if (ret)
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goto unlock;
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if (!mask)
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ret = regmap_write(st->regmap, reg, val);
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else
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ret = regmap_update_bits(st->regmap, reg, mask, val);
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if (ret)
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goto unlock;
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ret = regmap_update_bits(st->regmap, MAX31827_CONFIGURATION_REG,
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MAX31827_CONFIGURATION_CNV_RATE_MASK,
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cnv_rate);
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unlock:
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mutex_unlock(&st->lock);
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return ret;
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}
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static int write_alarm_val(struct max31827_state *st, unsigned int reg,
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long val)
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{
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val = MAX31827_M_DGR_TO_16_BIT(val);
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return shutdown_write(st, reg, 0, val);
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}
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static umode_t max31827_is_visible(const void *state,
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enum hwmon_sensor_types type, u32 attr,
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int channel)
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{
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if (type == hwmon_temp) {
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switch (attr) {
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case hwmon_temp_enable:
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case hwmon_temp_max:
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case hwmon_temp_min:
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case hwmon_temp_max_hyst:
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case hwmon_temp_min_hyst:
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return 0644;
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case hwmon_temp_input:
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case hwmon_temp_min_alarm:
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case hwmon_temp_max_alarm:
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return 0444;
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default:
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return 0;
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}
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} else if (type == hwmon_chip) {
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if (attr == hwmon_chip_update_interval)
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return 0644;
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}
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return 0;
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}
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static int max31827_read(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long *val)
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{
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struct max31827_state *st = dev_get_drvdata(dev);
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unsigned int uval;
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int ret = 0;
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switch (type) {
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case hwmon_temp:
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switch (attr) {
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case hwmon_temp_enable:
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ret = regmap_read(st->regmap,
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MAX31827_CONFIGURATION_REG, &uval);
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if (ret)
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break;
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uval = FIELD_GET(MAX31827_CONFIGURATION_1SHOT_MASK |
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MAX31827_CONFIGURATION_CNV_RATE_MASK,
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uval);
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*val = !!uval;
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break;
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case hwmon_temp_input:
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mutex_lock(&st->lock);
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if (!st->enable) {
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/*
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* This operation requires mutex protection,
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* because the chip configuration should not
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* be changed during the conversion process.
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*/
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ret = regmap_update_bits(st->regmap,
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MAX31827_CONFIGURATION_REG,
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MAX31827_CONFIGURATION_1SHOT_MASK,
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1);
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if (ret) {
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mutex_unlock(&st->lock);
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return ret;
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}
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msleep(max31827_conv_times[st->resolution]);
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}
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/*
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* For 12-bit resolution the conversion time is 140 ms,
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* thus an additional 15 ms is needed to complete the
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* conversion: 125 ms + 15 ms = 140 ms
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*/
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if (max31827_resolutions[st->resolution] == 12 &&
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st->update_interval == 125)
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usleep_range(15000, 20000);
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ret = regmap_read(st->regmap, MAX31827_T_REG, &uval);
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mutex_unlock(&st->lock);
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if (ret)
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break;
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*val = MAX31827_16_BIT_TO_M_DGR(uval);
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break;
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case hwmon_temp_max:
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ret = regmap_read(st->regmap, MAX31827_TH_REG, &uval);
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if (ret)
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break;
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*val = MAX31827_16_BIT_TO_M_DGR(uval);
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break;
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case hwmon_temp_max_hyst:
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ret = regmap_read(st->regmap, MAX31827_TH_HYST_REG,
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&uval);
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if (ret)
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break;
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*val = MAX31827_16_BIT_TO_M_DGR(uval);
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break;
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case hwmon_temp_max_alarm:
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ret = regmap_read(st->regmap,
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MAX31827_CONFIGURATION_REG, &uval);
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if (ret)
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break;
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*val = FIELD_GET(MAX31827_CONFIGURATION_O_TEMP_STAT_MASK,
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uval);
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break;
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case hwmon_temp_min:
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ret = regmap_read(st->regmap, MAX31827_TL_REG, &uval);
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if (ret)
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break;
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*val = MAX31827_16_BIT_TO_M_DGR(uval);
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break;
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case hwmon_temp_min_hyst:
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ret = regmap_read(st->regmap, MAX31827_TL_HYST_REG,
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&uval);
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if (ret)
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break;
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*val = MAX31827_16_BIT_TO_M_DGR(uval);
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break;
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case hwmon_temp_min_alarm:
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ret = regmap_read(st->regmap,
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MAX31827_CONFIGURATION_REG, &uval);
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if (ret)
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break;
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*val = FIELD_GET(MAX31827_CONFIGURATION_U_TEMP_STAT_MASK,
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uval);
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break;
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default:
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ret = -EOPNOTSUPP;
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break;
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}
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break;
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case hwmon_chip:
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if (attr == hwmon_chip_update_interval) {
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ret = regmap_read(st->regmap,
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MAX31827_CONFIGURATION_REG, &uval);
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if (ret)
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break;
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uval = FIELD_GET(MAX31827_CONFIGURATION_CNV_RATE_MASK,
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uval);
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*val = max31827_conversions[uval];
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}
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break;
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default:
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ret = -EOPNOTSUPP;
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break;
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}
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return ret;
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}
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static int max31827_write(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long val)
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{
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struct max31827_state *st = dev_get_drvdata(dev);
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int res = 1;
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int ret;
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switch (type) {
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case hwmon_temp:
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switch (attr) {
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case hwmon_temp_enable:
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if (val >> 1)
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return -EINVAL;
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mutex_lock(&st->lock);
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/**
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* The chip should not be enabled while a conversion is
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* performed. Neither should the chip be enabled when
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* the alarm values are changed.
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*/
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st->enable = val;
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ret = regmap_update_bits(st->regmap,
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MAX31827_CONFIGURATION_REG,
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MAX31827_CONFIGURATION_1SHOT_MASK |
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MAX31827_CONFIGURATION_CNV_RATE_MASK,
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MAX31827_DEVICE_ENABLE(val));
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mutex_unlock(&st->lock);
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return ret;
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case hwmon_temp_max:
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return write_alarm_val(st, MAX31827_TH_REG, val);
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case hwmon_temp_max_hyst:
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return write_alarm_val(st, MAX31827_TH_HYST_REG, val);
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case hwmon_temp_min:
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return write_alarm_val(st, MAX31827_TL_REG, val);
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case hwmon_temp_min_hyst:
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return write_alarm_val(st, MAX31827_TL_HYST_REG, val);
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default:
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return -EOPNOTSUPP;
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}
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case hwmon_chip:
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if (attr == hwmon_chip_update_interval) {
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if (!st->enable)
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return -EINVAL;
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/*
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* Convert the desired conversion rate into register
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* bits. res is already initialized with 1.
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*
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* This was inspired by lm73 driver.
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*/
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while (res < ARRAY_SIZE(max31827_conversions) &&
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val < max31827_conversions[res])
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res++;
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if (res == ARRAY_SIZE(max31827_conversions))
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res = ARRAY_SIZE(max31827_conversions) - 1;
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res = FIELD_PREP(MAX31827_CONFIGURATION_CNV_RATE_MASK,
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res);
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ret = regmap_update_bits(st->regmap,
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MAX31827_CONFIGURATION_REG,
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MAX31827_CONFIGURATION_CNV_RATE_MASK,
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res);
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if (ret)
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return ret;
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st->update_interval = val;
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}
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static ssize_t temp1_resolution_show(struct device *dev,
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struct device_attribute *devattr,
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char *buf)
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{
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struct max31827_state *st = dev_get_drvdata(dev);
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unsigned int val;
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int ret;
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ret = regmap_read(st->regmap, MAX31827_CONFIGURATION_REG, &val);
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if (ret)
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return ret;
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val = FIELD_GET(MAX31827_CONFIGURATION_RESOLUTION_MASK, val);
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return scnprintf(buf, PAGE_SIZE, "%u\n", max31827_resolutions[val]);
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}
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static ssize_t temp1_resolution_store(struct device *dev,
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struct device_attribute *devattr,
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const char *buf, size_t count)
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{
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struct max31827_state *st = dev_get_drvdata(dev);
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unsigned int idx = 0;
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unsigned int val;
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int ret;
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ret = kstrtouint(buf, 10, &val);
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if (ret)
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return ret;
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/*
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* Convert the desired resolution into register
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* bits. idx is already initialized with 0.
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*
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* This was inspired by lm73 driver.
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*/
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while (idx < ARRAY_SIZE(max31827_resolutions) &&
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val < max31827_resolutions[idx])
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idx++;
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if (idx == ARRAY_SIZE(max31827_resolutions))
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idx = ARRAY_SIZE(max31827_resolutions) - 1;
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st->resolution = idx;
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ret = shutdown_write(st, MAX31827_CONFIGURATION_REG,
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MAX31827_CONFIGURATION_RESOLUTION_MASK,
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FIELD_PREP(MAX31827_CONFIGURATION_RESOLUTION_MASK,
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idx));
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return ret ? ret : count;
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}
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static DEVICE_ATTR_RW(temp1_resolution);
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static struct attribute *max31827_attrs[] = {
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&dev_attr_temp1_resolution.attr,
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NULL
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};
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ATTRIBUTE_GROUPS(max31827);
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static const struct i2c_device_id max31827_i2c_ids[] = {
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{ "max31827", max31827 },
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{ "max31828", max31828 },
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{ "max31829", max31829 },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, max31827_i2c_ids);
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static int max31827_init_client(struct max31827_state *st,
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struct device *dev)
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{
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struct fwnode_handle *fwnode;
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unsigned int res = 0;
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u32 data, lsb_idx;
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enum chips type;
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bool prop;
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int ret;
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fwnode = dev_fwnode(dev);
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st->enable = true;
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res |= MAX31827_DEVICE_ENABLE(1);
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res |= MAX31827_CONFIGURATION_RESOLUTION_MASK;
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prop = fwnode_property_read_bool(fwnode, "adi,comp-int");
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res |= FIELD_PREP(MAX31827_CONFIGURATION_COMP_INT_MASK, prop);
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prop = fwnode_property_read_bool(fwnode, "adi,timeout-enable");
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res |= FIELD_PREP(MAX31827_CONFIGURATION_TIMEOUT_MASK, !prop);
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type = (enum chips)(uintptr_t)device_get_match_data(dev);
|
|
|
|
if (fwnode_property_present(fwnode, "adi,alarm-pol")) {
|
|
ret = fwnode_property_read_u32(fwnode, "adi,alarm-pol", &data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
res |= FIELD_PREP(MAX31827_CONFIGURATION_ALRM_POL_MASK, !!data);
|
|
} else {
|
|
/*
|
|
* Set default value.
|
|
*/
|
|
switch (type) {
|
|
case max31827:
|
|
case max31828:
|
|
res |= FIELD_PREP(MAX31827_CONFIGURATION_ALRM_POL_MASK,
|
|
MAX31827_ALRM_POL_LOW);
|
|
break;
|
|
case max31829:
|
|
res |= FIELD_PREP(MAX31827_CONFIGURATION_ALRM_POL_MASK,
|
|
MAX31827_ALRM_POL_HIGH);
|
|
break;
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
if (fwnode_property_present(fwnode, "adi,fault-q")) {
|
|
ret = fwnode_property_read_u32(fwnode, "adi,fault-q", &data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Convert the desired fault queue into register bits.
|
|
*/
|
|
if (data != 0)
|
|
lsb_idx = __ffs(data);
|
|
|
|
if (hweight32(data) != 1 || lsb_idx > 4) {
|
|
dev_err(dev, "Invalid data in adi,fault-q\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
res |= FIELD_PREP(MAX31827_CONFIGURATION_FLT_Q_MASK, lsb_idx);
|
|
} else {
|
|
/*
|
|
* Set default value.
|
|
*/
|
|
switch (type) {
|
|
case max31827:
|
|
res |= FIELD_PREP(MAX31827_CONFIGURATION_FLT_Q_MASK,
|
|
MAX31827_FLT_Q_1);
|
|
break;
|
|
case max31828:
|
|
case max31829:
|
|
res |= FIELD_PREP(MAX31827_CONFIGURATION_FLT_Q_MASK,
|
|
MAX31827_FLT_Q_4);
|
|
break;
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
return regmap_write(st->regmap, MAX31827_CONFIGURATION_REG, res);
|
|
}
|
|
|
|
static const struct hwmon_channel_info *max31827_info[] = {
|
|
HWMON_CHANNEL_INFO(temp, HWMON_T_ENABLE | HWMON_T_INPUT | HWMON_T_MIN |
|
|
HWMON_T_MIN_HYST | HWMON_T_MIN_ALARM |
|
|
HWMON_T_MAX | HWMON_T_MAX_HYST |
|
|
HWMON_T_MAX_ALARM),
|
|
HWMON_CHANNEL_INFO(chip, HWMON_C_UPDATE_INTERVAL),
|
|
NULL,
|
|
};
|
|
|
|
static const struct hwmon_ops max31827_hwmon_ops = {
|
|
.is_visible = max31827_is_visible,
|
|
.read = max31827_read,
|
|
.write = max31827_write,
|
|
};
|
|
|
|
static const struct hwmon_chip_info max31827_chip_info = {
|
|
.ops = &max31827_hwmon_ops,
|
|
.info = max31827_info,
|
|
};
|
|
|
|
static int max31827_probe(struct i2c_client *client)
|
|
{
|
|
struct device *dev = &client->dev;
|
|
struct device *hwmon_dev;
|
|
struct max31827_state *st;
|
|
int err;
|
|
|
|
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA))
|
|
return -EOPNOTSUPP;
|
|
|
|
st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
|
|
if (!st)
|
|
return -ENOMEM;
|
|
|
|
mutex_init(&st->lock);
|
|
|
|
st->regmap = devm_regmap_init_i2c(client, &max31827_regmap);
|
|
if (IS_ERR(st->regmap))
|
|
return dev_err_probe(dev, PTR_ERR(st->regmap),
|
|
"Failed to allocate regmap.\n");
|
|
|
|
err = devm_regulator_get_enable(dev, "vref");
|
|
if (err)
|
|
return dev_err_probe(dev, err, "failed to enable regulator\n");
|
|
|
|
err = max31827_init_client(st, dev);
|
|
if (err)
|
|
return err;
|
|
|
|
hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, st,
|
|
&max31827_chip_info,
|
|
max31827_groups);
|
|
|
|
return PTR_ERR_OR_ZERO(hwmon_dev);
|
|
}
|
|
|
|
static const struct of_device_id max31827_of_match[] = {
|
|
{
|
|
.compatible = "adi,max31827",
|
|
.data = (void *)max31827
|
|
},
|
|
{
|
|
.compatible = "adi,max31828",
|
|
.data = (void *)max31828
|
|
},
|
|
{
|
|
.compatible = "adi,max31829",
|
|
.data = (void *)max31829
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, max31827_of_match);
|
|
|
|
static struct i2c_driver max31827_driver = {
|
|
.driver = {
|
|
.name = "max31827",
|
|
.of_match_table = max31827_of_match,
|
|
},
|
|
.probe = max31827_probe,
|
|
.id_table = max31827_i2c_ids,
|
|
};
|
|
module_i2c_driver(max31827_driver);
|
|
|
|
MODULE_AUTHOR("Daniel Matyas <daniel.matyas@analog.com>");
|
|
MODULE_DESCRIPTION("Maxim MAX31827 low-power temperature switch driver");
|
|
MODULE_LICENSE("GPL");
|