85b0e13b19
This adds Rockchip RK3588 AHCI binding. In order to narrow down the allowed clocks without bloating the generic binding, the description of Rockchip's AHCI controllers has been moved to its own file. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
81 lines
1.6 KiB
YAML
81 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DWC AHCI SATA controller
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maintainers:
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- Serge Semin <fancer.lancer@gmail.com>
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description:
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This document defines device tree bindings for the generic Synopsys DWC
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implementation of the AHCI SATA controller.
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select:
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properties:
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compatible:
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enum:
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- snps,dwc-ahci
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- snps,spear-ahci
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required:
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- compatible
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allOf:
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- $ref: snps,dwc-ahci-common.yaml#
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properties:
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compatible:
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oneOf:
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- description: Synopsys AHCI SATA-compatible devices
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const: snps,dwc-ahci
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- description: SPEAr1340 AHCI SATA device
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const: snps,spear-ahci
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patternProperties:
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"^sata-port@[0-9a-e]$":
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$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/ata/ahci.h>
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sata@122f0000 {
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compatible = "snps,dwc-ahci";
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reg = <0x122F0000 0x1ff>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock1>, <&clock2>;
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clock-names = "aclk", "ref";
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phys = <&sata_phy>;
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phy-names = "sata-phy";
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ports-implemented = <0x1>;
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sata-port@0 {
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reg = <0>;
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hba-port-cap = <HBA_PORT_FBSCP>;
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snps,tx-ts-max = <512>;
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snps,rx-ts-max = <512>;
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};
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};
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...
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