14dde0746e
Add dt-bindings for the CSI IP found inside the RZ/V2M SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/Message-Id: <20230622113341.657842-2-fabrizio.castro.jz@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
71 lines
1.5 KiB
YAML
71 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Renesas RZ/V2M Clocked Serial Interface (CSI)
|
|
|
|
maintainers:
|
|
- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
|
|
- Geert Uytterhoeven <geert+renesas@glider.be>
|
|
|
|
allOf:
|
|
- $ref: spi-controller.yaml#
|
|
|
|
properties:
|
|
compatible:
|
|
const: renesas,rzv2m-csi
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
items:
|
|
- description: The clock used to generate the output clock (CSICLK)
|
|
- description: Internal clock to access the registers (PCLK)
|
|
|
|
clock-names:
|
|
items:
|
|
- const: csiclk
|
|
- const: pclk
|
|
|
|
resets:
|
|
maxItems: 1
|
|
|
|
power-domains:
|
|
maxItems: 1
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupts
|
|
- clocks
|
|
- clock-names
|
|
- resets
|
|
- power-domains
|
|
- '#address-cells'
|
|
- '#size-cells'
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/clock/r9a09g011-cpg.h>
|
|
csi4: spi@a4020200 {
|
|
compatible = "renesas,rzv2m-csi";
|
|
reg = <0xa4020200 0x80>;
|
|
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
|
|
<&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
|
|
clock-names = "csiclk", "pclk";
|
|
resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
|
|
power-domains = <&cpg>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|