2bfdd113d0
The conversion of the spi-imx driver to use GPIO descriptors
in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors")
helped to detect the following SPI chipselect polarity mismatch on an
imx6q-sabresd:
[ 4.854337] m25p80@0 enforce active low on chipselect handle
Prior to the above commit, the chipselect polarity passed via cs-gpios
property was ignored and considered active-low.
The reason for such mismatch is clearly explained in the comments inside
drivers/gpio/gpiolib-of.c:
* SPI children have active low chip selects
* by default. This can be specified negatively
* by just omitting "spi-cs-high" in the
* device node, or actively by tagging on
* GPIO_ACTIVE_LOW as flag in the device
* tree. If the line is simultaneously
* tagged as active low in the device tree
* and has the "spi-cs-high" set, we get a
* conflict and the "spi-cs-high" flag will
* take precedence.
To properly represent the SPI chipselect polarity, change it to active-low
when the "spi-cs-high" property is absent.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
98 lines
2.0 KiB
Plaintext
98 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
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* and Markus Pargmann, Pengutronix
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*/
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/dts-v1/;
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#include "imx27.dtsi"
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/ {
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model = "Phytec pca100";
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compatible = "phytec,imx27-pca100", "fsl,imx27";
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memory@a0000000 {
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device_type = "memory";
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reg = <0xa0000000 0x08000000>; /* 128MB */
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};
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};
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&cspi1 {
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cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>,
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<&gpio4 27 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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at24@52 {
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compatible = "atmel,24c32";
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pagesize = <32>;
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reg = <0x52>;
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};
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};
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&iomuxc {
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imx27-phycard-s-som {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX27_PAD_SD3_CMD__FEC_TXD0 0x0
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MX27_PAD_SD3_CLK__FEC_TXD1 0x0
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MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
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MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
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MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
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MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
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MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
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MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
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MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
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MX27_PAD_ATA_DATA7__FEC_MDC 0x0
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MX27_PAD_ATA_DATA8__FEC_CRS 0x0
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MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
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MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
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MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
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MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
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MX27_PAD_ATA_DATA13__FEC_COL 0x0
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MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
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MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
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MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
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>;
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};
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pinctrl_nfc: nfcgrp {
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fsl,pins = <
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MX27_PAD_NFRB__NFRB 0x0
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MX27_PAD_NFCLE__NFCLE 0x0
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MX27_PAD_NFWP_B__NFWP_B 0x0
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MX27_PAD_NFCE_B__NFCE_B 0x0
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MX27_PAD_NFALE__NFALE 0x0
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MX27_PAD_NFRE_B__NFRE_B 0x0
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MX27_PAD_NFWE_B__NFWE_B 0x0
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>;
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};
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};
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};
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&nfc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nfc>;
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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nand-on-flash-bbt;
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status = "okay";
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};
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