e606ca36bb
Add a fresh documented implementation of the ATU Move operation, and use it to replace the current ATU Remove operation. Note that not all Marvell switch chip support the ATU Move operation. For those supporting it, the number of bits used to mask the destination port may vary. 6352 and such use 4-bit, while 6390 use 5-bit. Thus add a new atu_move_port_mask member in the info structure to describe the presence and variant of ATU Move operation. Note that the ATU Move operation is not documented in the 6185 datasheet but the chip does support the operation. All remaining _mv88e6xxx_atu_* functions are now unused as well as the MV88E6XXX_FLAG_G1_ATU_FID flag, thus remove them. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
301 lines
6.9 KiB
C
301 lines
6.9 KiB
C
/*
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* Marvell 88E6xxx Address Translation Unit (ATU) support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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* Copyright (c) 2017 Savoir-faire Linux, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "mv88e6xxx.h"
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#include "global1.h"
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/* Offset 0x01: ATU FID Register */
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static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid)
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{
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return mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid & 0xfff);
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}
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/* Offset 0x0A: ATU Control Register */
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int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
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if (err)
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return err;
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if (learn2all)
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val |= GLOBAL_ATU_CONTROL_LEARN2ALL;
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else
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val &= ~GLOBAL_ATU_CONTROL_LEARN2ALL;
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return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
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}
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int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
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unsigned int msecs)
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{
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const unsigned int coeff = chip->info->age_time_coeff;
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const unsigned int min = 0x01 * coeff;
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const unsigned int max = 0xff * coeff;
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u8 age_time;
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u16 val;
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int err;
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if (msecs < min || msecs > max)
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return -ERANGE;
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/* Round to nearest multiple of coeff */
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age_time = (msecs + coeff / 2) / coeff;
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err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
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if (err)
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return err;
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/* AgeTime is 11:4 bits */
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val &= ~0xff0;
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val |= age_time << 4;
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return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
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}
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/* Offset 0x0B: ATU Operation Register */
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static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
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}
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static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op)
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{
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u16 val;
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int err;
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/* FID bits are dispatched all around gradually as more are supported */
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if (mv88e6xxx_num_databases(chip) > 256) {
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err = mv88e6xxx_g1_atu_fid_write(chip, fid);
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if (err)
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return err;
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} else {
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if (mv88e6xxx_num_databases(chip) > 16) {
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/* ATU DBNum[7:4] are located in ATU Control 15:12 */
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err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
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if (err)
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return err;
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val = (val & 0x0fff) | ((fid << 8) & 0xf000);
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err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
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if (err)
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return err;
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}
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/* ATU DBNum[3:0] are located in ATU Operation 3:0 */
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op |= fid & 0xf;
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}
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err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, op);
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if (err)
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return err;
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return mv88e6xxx_g1_atu_op_wait(chip);
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}
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/* Offset 0x0C: ATU Data Register */
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static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_atu_entry *entry)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
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if (err)
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return err;
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entry->state = val & 0xf;
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if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
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if (val & GLOBAL_ATU_DATA_TRUNK)
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entry->trunk = true;
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entry->portv_trunkid = (val >> 4) & mv88e6xxx_port_mask(chip);
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}
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return 0;
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}
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static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_atu_entry *entry)
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{
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u16 data = entry->state & 0xf;
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if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
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if (entry->trunk)
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data |= GLOBAL_ATU_DATA_TRUNK;
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data |= (entry->portv_trunkid & mv88e6xxx_port_mask(chip)) << 4;
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}
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return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
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}
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/* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
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* Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
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* Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
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*/
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static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_atu_entry *entry)
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{
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u16 val;
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int i, err;
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for (i = 0; i < 3; i++) {
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err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
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if (err)
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return err;
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entry->mac[i * 2] = val >> 8;
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entry->mac[i * 2 + 1] = val & 0xff;
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}
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return 0;
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}
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static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_atu_entry *entry)
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{
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u16 val;
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int i, err;
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for (i = 0; i < 3; i++) {
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val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1];
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err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i, val);
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if (err)
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return err;
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}
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return 0;
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}
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/* Address Translation Unit operations */
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int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
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struct mv88e6xxx_atu_entry *entry)
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{
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int err;
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err = mv88e6xxx_g1_atu_op_wait(chip);
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if (err)
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return err;
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/* Write the MAC address to iterate from only once */
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if (entry->state == GLOBAL_ATU_DATA_STATE_UNUSED) {
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err = mv88e6xxx_g1_atu_mac_write(chip, entry);
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if (err)
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return err;
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}
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err = mv88e6xxx_g1_atu_op(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
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if (err)
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return err;
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err = mv88e6xxx_g1_atu_data_read(chip, entry);
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if (err)
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return err;
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return mv88e6xxx_g1_atu_mac_read(chip, entry);
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}
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int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
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struct mv88e6xxx_atu_entry *entry)
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{
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int err;
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err = mv88e6xxx_g1_atu_op_wait(chip);
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if (err)
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return err;
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err = mv88e6xxx_g1_atu_mac_write(chip, entry);
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if (err)
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return err;
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err = mv88e6xxx_g1_atu_data_write(chip, entry);
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if (err)
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return err;
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return mv88e6xxx_g1_atu_op(chip, fid, GLOBAL_ATU_OP_LOAD_DB);
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}
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static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid,
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struct mv88e6xxx_atu_entry *entry,
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bool all)
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{
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u16 op;
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int err;
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err = mv88e6xxx_g1_atu_op_wait(chip);
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if (err)
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return err;
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err = mv88e6xxx_g1_atu_data_write(chip, entry);
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if (err)
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return err;
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/* Flush/Move all or non-static entries from all or a given database */
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if (all && fid)
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op = GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB;
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else if (fid)
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op = GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
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else if (all)
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op = GLOBAL_ATU_OP_FLUSH_MOVE_ALL;
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else
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op = GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
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return mv88e6xxx_g1_atu_op(chip, fid, op);
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}
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int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all)
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{
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struct mv88e6xxx_atu_entry entry = {
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.state = 0, /* Null EntryState means Flush */
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};
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return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
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}
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static int mv88e6xxx_g1_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
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int from_port, int to_port, bool all)
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{
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struct mv88e6xxx_atu_entry entry = { 0 };
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unsigned long mask;
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int shift;
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if (!chip->info->atu_move_port_mask)
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return -EOPNOTSUPP;
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mask = chip->info->atu_move_port_mask;
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shift = bitmap_weight(&mask, 16);
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entry.state = 0xf, /* Full EntryState means Move */
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entry.portv_trunkid = from_port & mask;
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entry.portv_trunkid |= (to_port & mask) << shift;
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return mv88e6xxx_g1_atu_flushmove(chip, fid, &entry, all);
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}
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int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
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bool all)
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{
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int from_port = port;
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int to_port = chip->info->atu_move_port_mask;
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return mv88e6xxx_g1_atu_move(chip, fid, from_port, to_port, all);
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}
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