Yong Wu e6dec92308 iommu/mediatek: Add mt2712 IOMMU support ... The M4U IP blocks in mt2712 is MTK's generation2 M4U which use the ARM Short-descriptor like mt8173, and most of the HW registers are the same. The difference is that there are 2 M4U HWs in mt2712 while there's only one in mt8173. The purpose of 2 M4U HWs is for balance the bandwidth. Normally if there are 2 M4U HWs, there should be 2 iommu domains, each M4U has a iommu domain. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>		2017-08-22 16:37:58 +02:00
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arc	ARCv2: IDU-intc: Use build registers for getting numbers of interrupts	2017-02-06 09:37:57 -08:00
at91	ARM: at91: define LPDDR types	2017-01-16 23:21:29 +01:00
bcm2835	staging: vc04_services: fix up rpi firmware functions	2016-10-16 10:26:12 +02:00
brcmstb
fsl	net/wan/fsl_ucc_hdlc: add hdlc-bus support	2017-05-18 10:28:39 -04:00
imx	ARM: imx6: fix static declaration in include/soc/imx/cpuidle.h	2016-06-21 14:35:29 +08:00
mediatek	iommu/mediatek: Add mt2712 IOMMU support	2017-08-22 16:37:58 +02:00
nps	soc: Support for NPS HW scheduling	2016-11-30 11:54:25 -08:00
rockchip	soc: rockchip: add header for ddr rate SIP interface	2016-08-31 18:53:24 +02:00
sa1100
tegra	soc/tegra: bpmp: Implement generic PM domains	2017-06-13 15:23:29 +02:00