Dirk Behme e8094b2c17 ARM i.MX6: Fix ldb_di clock selection
According to the recent i.MX6 Quad technical reference manual, mode 0x4 (100b)
of the CCM_CS2DCR register (address 0x020C402C) bits [11-9] and [14-12] select
the PLL3 clock, and not the PLL3 PFD1 540M clock. In our code, the PLL3 root
clock is named 'pll3_usb_otg', select this instead of the 540M clock.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-09 19:48:09 +08:00
..
2013-03-18 08:17:14 -07:00
2013-02-28 20:09:24 -08:00
2013-02-21 14:58:40 -08:00
2013-02-21 14:58:40 -08:00
2013-02-21 15:27:22 -08:00
2013-02-21 14:58:40 -08:00
2013-02-28 20:00:40 -08:00
2012-11-12 23:22:54 +01:00
2013-02-21 15:40:16 -08:00