694ff00c9b
Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350 etc. requires interconnect path between the engine and memory to be explicitly enabled and bandwidth set prior to any operations. Add support in the qce core to enable the interconnect path appropriately. Tested-by: Jordan Crouse <jorcrous@amazon.com> Signed-off-by: Thara Gopinath <thara.gopinath@gmail.com> [Bhupesh: Make header file inclusion alphabetical and use devm_of_icc_get()] Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> [vladimir: moved icc bandwidth setup closer to its acquisition] Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
62 lines
1.8 KiB
C
62 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CORE_H_
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#define _CORE_H_
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#include "dma.h"
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/**
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* struct qce_device - crypto engine device structure
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* @queue: crypto request queue
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* @lock: the lock protects queue and req
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* @done_tasklet: done tasklet object
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* @req: current active request
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* @result: result of current transform
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* @base: virtual IO base
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* @dev: pointer to device structure
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* @core: core device clock
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* @iface: interface clock
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* @bus: bus clock
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* @dma: pointer to dma data
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* @burst_size: the crypto burst size
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* @pipe_pair_id: which pipe pair id the device using
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* @async_req_enqueue: invoked by every algorithm to enqueue a request
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* @async_req_done: invoked by every algorithm to finish its request
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*/
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struct qce_device {
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struct crypto_queue queue;
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spinlock_t lock;
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struct tasklet_struct done_tasklet;
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struct crypto_async_request *req;
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int result;
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void __iomem *base;
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struct device *dev;
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struct clk *core, *iface, *bus;
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struct icc_path *mem_path;
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struct qce_dma_data dma;
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int burst_size;
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unsigned int pipe_pair_id;
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int (*async_req_enqueue)(struct qce_device *qce,
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struct crypto_async_request *req);
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void (*async_req_done)(struct qce_device *qce, int ret);
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};
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/**
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* struct qce_algo_ops - algorithm operations per crypto type
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* @type: should be CRYPTO_ALG_TYPE_XXX
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* @register_algs: invoked by core to register the algorithms
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* @unregister_algs: invoked by core to unregister the algorithms
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* @async_req_handle: invoked by core to handle enqueued request
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*/
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struct qce_algo_ops {
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u32 type;
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int (*register_algs)(struct qce_device *qce);
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void (*unregister_algs)(struct qce_device *qce);
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int (*async_req_handle)(struct crypto_async_request *async_req);
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};
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#endif /* _CORE_H_ */
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