e8c047b4a9
According to the ONFI specification, bit 0 of 'SDR timing mode support' (bytes 129-130) "shall be 1". That means the NAND supports at least timing mode 0. NAND chip Hynix H27U4G8F2GDA-BI (at least) is reading a 0 on this field which makes nand_choose_best_sdr_timings() return with error and the probe function to eventually fail. Given that sdr_timing_modes bit 0 must be 1 by specification, force it in case the NAND reports it is not set. This is a safe assumption because the mode 0 is the minimum (safer) set of timings that the NAND can work with. Signed-off-by: Hector Palacios <hector.palacios@digi.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230223165104.525852-1-hector.palacios@digi.com Link: https://lore.kernel.org/linux-mtd/20230310080609.1930869-1-hector.palacios@digi.com |
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| .. | ||
| onenand | ||
| raw | ||
| spi | ||
| bbt.c | ||
| core.c | ||
| ecc-mtk.c | ||
| ecc-mxic.c | ||
| ecc-sw-bch.c | ||
| ecc-sw-hamming.c | ||
| ecc.c | ||
| Kconfig | ||
| Makefile | ||