e97017f935
Rename the existing clkctrl data in preparation of upcoming clkdm based split for it. Once the DT data has transitioned also, the compat data can be removed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
78 lines
2.2 KiB
C
78 lines
2.2 KiB
C
/*
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* AM33XX Clock init
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*
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* Copyright (C) 2013 Texas Instruments, Inc
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* Tero Kristo (t-kristo@ti.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/ti.h>
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#include <dt-bindings/clock/am3.h>
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#include "clock.h"
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static const char *enable_init_clks[] = {
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"dpll_ddr_m2_ck",
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"dpll_mpu_m2_ck",
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"l3_gclk",
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"l4hs_gclk",
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"l4fw_gclk",
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"l4ls_gclk",
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/* Required for external peripherals like, Audio codecs */
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"clkout2_ck",
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};
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int __init am33xx_dt_clk_init(void)
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{
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struct clk *clk1, *clk2;
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ti_dt_clocks_register(am33xx_compat_clks);
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omap2_clk_disable_autoidle_all();
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ti_clk_add_aliases();
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omap2_clk_enable_init_clocks(enable_init_clks,
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ARRAY_SIZE(enable_init_clks));
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/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
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* physically present, in such a case HWMOD enabling of
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* clock would be failure with default parent. And timer
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* probe thinks clock is already enabled, this leads to
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* crash upon accessing timer 3 & 6 registers in probe.
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* Fix by setting parent of both these timers to master
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* oscillator clock.
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*/
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clk1 = clk_get_sys(NULL, "sys_clkin_ck");
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clk2 = clk_get_sys(NULL, "timer3_fck");
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clk_set_parent(clk2, clk1);
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clk2 = clk_get_sys(NULL, "timer6_fck");
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clk_set_parent(clk2, clk1);
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/*
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* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
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* the design/spec, so as a result, for example, timer which supposed
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* to get expired @60Sec, but will expire somewhere ~@40Sec, which is
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* not expected by any use-case, so change WDT1 clock source to PRCM
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* 32KHz clock.
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*/
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clk1 = clk_get_sys(NULL, "wdt1_fck");
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clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
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clk_set_parent(clk1, clk2);
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return 0;
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}
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