b675542323
Now that we have a graph schema, rework the display related schemas to use it. Mostly this is adding a reference to graph.yaml and dropping duplicate parts from schemas. In panel-common.yaml, 'ports' is dropped. Any binding using 'ports' should be one with more than 1 port node, and the binding must define what each port is. Note that ti,sn65dsi86.yaml, ti,tfp410,yaml and toshiba,tc358768.yaml will need further updates to use video-interfaces.yaml once that lands. Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210104180724.2275098-1-robh@kernel.org
116 lines
3.1 KiB
YAML
116 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/thine,thc63lvd1024.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Thine Electronics THC63LVD1024 LVDS Decoder
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maintainers:
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- Jacopo Mondi <jacopo+renesas@jmondi.org>
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- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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description: |
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The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
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streams to parallel data outputs. The chip supports single/dual input/output
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modes, handling up to two LVDS input streams and up to two digital CMOS/TTL
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outputs.
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Single or dual operation mode, output data mapping and DDR output modes are
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configured through input signals and the chip does not expose any control
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bus.
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properties:
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compatible:
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const: thine,thc63lvd1024
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description: |
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The device can operate in single or dual input and output modes.
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When operating in single input mode, all pixels are received on port@0,
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and port@1 shall not contain any endpoint. In dual input mode,
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even-numbered pixels are received on port@0 and odd-numbered pixels on
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port@1, and both port@0 and port@1 shall contain endpoints.
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When operating in single output mode all pixels are output from the first
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CMOS/TTL port and port@3 shall not contain any endpoint. In dual output
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mode pixels are output from both CMOS/TTL ports and both port@2 and
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port@3 shall contain endpoints.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: First LVDS input port
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Second LVDS input port
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description: First digital CMOS/TTL parallel output
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port@3:
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$ref: /schemas/graph.yaml#/properties/port
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description: Second digital CMOS/TTL parallel output
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required:
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- port@0
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- port@2
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oe-gpios:
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maxItems: 1
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description: Output enable GPIO signal, pin name "OE", active high.
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powerdown-gpios:
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maxItems: 1
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description: Power down GPIO signal, pin name "/PDWN", active low.
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vcc-supply:
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description:
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Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and
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digital circuitry.
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required:
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- compatible
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- ports
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- vcc-supply
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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lvds-decoder {
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compatible = "thine,thc63lvd1024";
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vcc-supply = <®_lvds_vcc>;
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powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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lvds_dec_in_0: endpoint {
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remote-endpoint = <&lvds_out>;
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};
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};
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port@2 {
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reg = <2>;
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lvds_dec_out_2: endpoint {
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remote-endpoint = <&adv7511_in>;
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};
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};
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};
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};
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...
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