0c0f65c6dd
Currently we do not differentiate between the various users of the qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one compatible string but, the hardware does have some significant differences in the number of clocks. To facilitate documenting the clocks add the following compatible strings - qcom,apq8064-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl - qcom,msm8974-dsi-ctrl - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl - qcom,sm8450-dsi-ctrl - qcom,sm8550-dsi-ctrl - qcom,qcm2290-dsi-ctrl Deprecate qcom,dsi-ctrl-6g-qcm2290 in favour of the desired format while we do so. Several MDSS yaml files exist which document the dsi sub-node. For each existing SoC MDSS yaml, provide the right dsi compat string. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519078/ Link: https://lore.kernel.org/r/20230118171621.102694-2-bryan.odonoghue@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
208 lines
4.5 KiB
YAML
208 lines
4.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Mobile Display SubSystem (MDSS)
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maintainers:
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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- Rob Clark <robdclark@gmail.com>
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description:
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This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
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encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
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properties:
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$nodename:
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pattern: "^display-subsystem@[0-9a-f]+$"
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compatible:
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enum:
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- qcom,mdss
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reg:
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minItems: 2
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maxItems: 3
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reg-names:
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minItems: 2
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items:
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- const: mdss_phys
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- const: vbif_phys
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- const: vbif_nrt_phys
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells":
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const: 1
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power-domains:
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maxItems: 1
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description: |
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The MDSS power domain provided by GCC
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clocks:
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oneOf:
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- minItems: 3
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items:
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- description: Display abh clock
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- description: Display axi clock
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- description: Display vsync clock
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- description: Display core clock
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- minItems: 1
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items:
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- description: Display abh clock
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- description: Display core clock
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clock-names:
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oneOf:
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- minItems: 3
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items:
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- const: iface
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- const: bus
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- const: vsync
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- const: core
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- minItems: 1
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items:
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- const: iface
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- const: core
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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resets:
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items:
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- description: MDSS_CORE reset
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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- power-domains
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- clocks
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- clock-names
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- "#address-cells"
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- "#size-cells"
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- ranges
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patternProperties:
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"^display-controller@[1-9a-f][0-9a-f]*$":
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type: object
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properties:
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compatible:
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contains:
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const: qcom,mdp5
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"^dsi@[1-9a-f][0-9a-f]*$":
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type: object
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properties:
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compatible:
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contains:
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const: qcom,mdss-dsi-ctrl
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"^phy@[1-9a-f][0-9a-f]*$":
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type: object
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properties:
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compatible:
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enum:
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- qcom,dsi-phy-14nm
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- qcom,dsi-phy-14nm-660
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- qcom,dsi-phy-14nm-8953
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- qcom,dsi-phy-20nm
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- qcom,dsi-phy-28nm-hpm
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- qcom,dsi-phy-28nm-lp
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- qcom,hdmi-phy-8084
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- qcom,hdmi-phy-8660
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- qcom,hdmi-phy-8960
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- qcom,hdmi-phy-8974
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- qcom,hdmi-phy-8996
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"^hdmi-tx@[1-9a-f][0-9a-f]*$":
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type: object
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properties:
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compatible:
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enum:
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- qcom,hdmi-tx-8084
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- qcom,hdmi-tx-8660
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- qcom,hdmi-tx-8960
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- qcom,hdmi-tx-8974
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- qcom,hdmi-tx-8994
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- qcom,hdmi-tx-8996
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8916.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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display-subsystem@1a00000 {
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compatible = "qcom,mdss";
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reg = <0x1a00000 0x1000>,
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<0x1ac8000 0x3000>;
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reg-names = "mdss_phys", "vbif_phys";
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power-domains = <&gcc MDSS_GDSC>;
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clocks = <&gcc GCC_MDSS_AHB_CLK>,
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<&gcc GCC_MDSS_AXI_CLK>,
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<&gcc GCC_MDSS_VSYNC_CLK>;
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clock-names = "iface",
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"bus",
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"vsync";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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display-controller@1a01000 {
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compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
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reg = <0x01a01000 0x89000>;
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reg-names = "mdp_phys";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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clocks = <&gcc GCC_MDSS_AHB_CLK>,
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<&gcc GCC_MDSS_AXI_CLK>,
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<&gcc GCC_MDSS_MDP_CLK>,
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<&gcc GCC_MDSS_VSYNC_CLK>;
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clock-names = "iface",
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"bus",
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"core",
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"vsync";
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iommus = <&apps_iommu 4>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdp5_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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};
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};
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};
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...
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