linux/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml
Robert Marko 4a8c14384f dt-bindings: net: ipq4019-mdio: document required clock-names
IPQ5018, IPQ6018 and IPQ8074 require clock-names to be set as driver is
requesting the clock based on it and not index, so document that and make
it required for the listed SoC-s.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221114194734.3287854-4-robimarko@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-11-17 21:14:38 -08:00

103 lines
1.9 KiB
YAML

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm IPQ40xx MDIO Controller
maintainers:
- Robert Marko <robert.marko@sartura.hr>
properties:
compatible:
oneOf:
- enum:
- qcom,ipq4019-mdio
- qcom,ipq5018-mdio
- items:
- enum:
- qcom,ipq6018-mdio
- qcom,ipq8074-mdio
- const: qcom,ipq4019-mdio
"#address-cells":
const: 1
"#size-cells":
const: 0
reg:
minItems: 1
maxItems: 2
description:
the first Address and length of the register set for the MDIO controller.
the second Address and length of the register for ethernet LDO, this second
address range is only required by the platform IPQ50xx.
clocks:
items:
- description: MDIO clock source frequency fixed to 100MHZ
clock-names:
items:
- const: gcc_mdio_ahb_clk
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
allOf:
- $ref: "mdio.yaml#"
- if:
properties:
compatible:
contains:
enum:
- qcom,ipq5018-mdio
- qcom,ipq6018-mdio
- qcom,ipq8074-mdio
then:
required:
- clocks
- clock-names
else:
properties:
clocks: false
clock-names: false
unevaluatedProperties: false
examples:
- |
mdio@90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,ipq4019-mdio";
reg = <0x90000 0x64>;
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
};
ethphy3: ethernet-phy@3 {
reg = <3>;
};
ethphy4: ethernet-phy@4 {
reg = <4>;
};
};