a96cbb146a
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5 Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx Signed-off-by: Stephen Boyd <sboyd@kernel.org>
505 lines
12 KiB
C
505 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "clk-regmap-phy-mux.h"
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#include "gdsc.h"
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#include "reset.h"
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enum {
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DT_BI_TCXO,
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DT_GCC_GPU_GPLL0_CLK_SRC,
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DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
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};
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enum {
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P_BI_TCXO,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_CC_PLL0_OUT_AUX2,
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P_GPU_CC_PLL0_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_AUX,
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P_GPU_CC_PLL1_OUT_MAIN,
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};
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static struct pll_vco default_vco[] = {
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{ 1000000000, 2000000000, 0 },
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};
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static struct pll_vco pll1_vco[] = {
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{ 500000000, 1000000000, 2 },
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};
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static const struct alpha_pll_config gpu_cc_pll0_config = {
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.l = 0x3e,
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.alpha = 0,
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.alpha_hi = 0x80,
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.vco_val = 0x0 << 20,
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.vco_mask = GENMASK(21, 20),
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.alpha_en_mask = BIT(24),
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.main_output_mask = BIT(0),
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.aux_output_mask = BIT(1),
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.aux2_output_mask = BIT(2),
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.config_ctl_val = 0x4001055b,
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.test_ctl_hi1_val = 0x1,
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};
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/* 1200MHz configuration */
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static struct clk_alpha_pll gpu_cc_pll0 = {
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.offset = 0x0,
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.vco_table = default_vco,
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.num_vco = ARRAY_SIZE(default_vco),
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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},
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};
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static const struct clk_div_table post_div_table_gpu_cc_pll0_out_aux2[] = {
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{ 0x0, 1 },
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{ }
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};
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static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_aux2 = {
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.offset = 0x0,
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.post_div_shift = 8,
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.post_div_table = post_div_table_gpu_cc_pll0_out_aux2,
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.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_aux2),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll0_out_aux2",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_cc_pll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_ops,
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},
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};
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/* 640MHz configuration */
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static const struct alpha_pll_config gpu_cc_pll1_config = {
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.l = 0x21,
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.alpha = 0x55555555,
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.alpha_hi = 0x55,
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.alpha_en_mask = BIT(24),
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.vco_val = 0x2 << 20,
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.vco_mask = GENMASK(21, 20),
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.main_output_mask = BIT(0),
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.aux_output_mask = BIT(1),
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.config_ctl_val = 0x4001055b,
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.test_ctl_hi1_val = 0x1,
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};
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static struct clk_alpha_pll gpu_cc_pll1 = {
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.offset = 0x100,
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.vco_table = pll1_vco,
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.num_vco = ARRAY_SIZE(pll1_vco),
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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},
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};
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static const struct clk_div_table post_div_table_gpu_cc_pll1_out_aux[] = {
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{ 0x0, 1 },
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{ }
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};
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static struct clk_alpha_pll_postdiv gpu_cc_pll1_out_aux = {
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.offset = 0x100,
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.post_div_shift = 15,
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.post_div_table = post_div_table_gpu_cc_pll1_out_aux,
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.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll1_out_aux),
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.width = 3,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1_out_aux",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_cc_pll1.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_ops,
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},
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};
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .index = P_BI_TCXO },
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{ .hw = &gpu_cc_pll0.clkr.hw },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
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};
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static const struct parent_map gpu_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
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{ P_GPU_CC_PLL1_OUT_AUX, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_1[] = {
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{ .index = P_BI_TCXO },
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{ .hw = &gpu_cc_pll0_out_aux2.clkr.hw },
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{ .hw = &gpu_cc_pll1_out_aux.clkr.hw },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
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F(320000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0),
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F(465000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0),
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F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(980000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
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.cmd_rcgr = 0x101c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_1,
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.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_gfx3d_clk_src",
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.parent_data = gpu_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch gpu_cc_ahb_clk = {
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.halt_reg = 0x1078,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1078,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_crc_ahb_clk = {
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.halt_reg = 0x107c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x107c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_crc_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gfx3d_clk = {
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.halt_reg = 0x10a4,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x10a4,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gfx3d_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gmu_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gmu_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
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.halt_reg = 0x108c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x108c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_snoc_dvm_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_aon_clk = {
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.halt_reg = 0x1004,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_aon_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_clk = {
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.halt_reg = 0x109c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x109c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_gx_cxo_clk = {
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.halt_reg = 0x1060,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1060,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_cxo_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_gx_gfx3d_clk = {
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.halt_reg = 0x1054,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x1054,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_gfx3d_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_sleep_clk = {
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.halt_reg = 0x1090,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1090,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_sleep_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
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.halt_reg = 0x5000,
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.halt_check = BRANCH_VOTED,
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.clkr = {
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.enable_reg = 0x5000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc gpu_cx_gdsc = {
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.gdscr = 0x106c,
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.gds_hw_ctrl = 0x1540,
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.pd = {
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.name = "gpu_cx_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = VOTABLE,
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};
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static struct gdsc gpu_gx_gdsc = {
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.gdscr = 0x100c,
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.clamp_io_ctrl = 0x1508,
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.resets = (unsigned int []){ GPU_GX_BCR },
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.reset_count = 1,
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.pd = {
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.name = "gpu_gx_gdsc",
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},
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.parent = &gpu_cx_gdsc.pd,
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.pwrsts = PWRSTS_OFF_ON,
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.flags = CLAMP_IO | SW_RESET | VOTABLE,
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};
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static struct clk_regmap *gpu_cc_sm6115_clocks[] = {
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[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
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[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
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[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
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[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
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[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
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[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
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[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
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[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
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[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
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[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
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[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
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[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
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[GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr,
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[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
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[GPU_CC_PLL1_OUT_AUX] = &gpu_cc_pll1_out_aux.clkr,
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[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
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[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
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|
};
|
|
|
|
static const struct qcom_reset_map gpu_cc_sm6115_resets[] = {
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[GPU_GX_BCR] = { 0x1008 },
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|
};
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|
|
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static struct gdsc *gpu_cc_sm6115_gdscs[] = {
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[GPU_CX_GDSC] = &gpu_cx_gdsc,
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[GPU_GX_GDSC] = &gpu_gx_gdsc,
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|
};
|
|
|
|
static const struct regmap_config gpu_cc_sm6115_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x9000,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct qcom_cc_desc gpu_cc_sm6115_desc = {
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.config = &gpu_cc_sm6115_regmap_config,
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|
.clks = gpu_cc_sm6115_clocks,
|
|
.num_clks = ARRAY_SIZE(gpu_cc_sm6115_clocks),
|
|
.resets = gpu_cc_sm6115_resets,
|
|
.num_resets = ARRAY_SIZE(gpu_cc_sm6115_resets),
|
|
.gdscs = gpu_cc_sm6115_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(gpu_cc_sm6115_gdscs),
|
|
};
|
|
|
|
static const struct of_device_id gpu_cc_sm6115_match_table[] = {
|
|
{ .compatible = "qcom,sm6115-gpucc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table);
|
|
|
|
static int gpu_cc_sm6115_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
|
|
regmap = qcom_cc_map(pdev, &gpu_cc_sm6115_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
|
clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
|
|
|
/* Set recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
|
|
qcom_branch_set_wakeup(regmap, gpu_cc_cx_gmu_clk, 0xf);
|
|
qcom_branch_set_sleep(regmap, gpu_cc_cx_gmu_clk, 0xf);
|
|
|
|
qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
|
|
qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
|
|
|
|
return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap);
|
|
}
|
|
|
|
static struct platform_driver gpu_cc_sm6115_driver = {
|
|
.probe = gpu_cc_sm6115_probe,
|
|
.driver = {
|
|
.name = "sm6115-gpucc",
|
|
.of_match_table = gpu_cc_sm6115_match_table,
|
|
},
|
|
};
|
|
module_platform_driver(gpu_cc_sm6115_driver);
|
|
|
|
MODULE_DESCRIPTION("QTI GPU_CC SM6115 Driver");
|
|
MODULE_LICENSE("GPL");
|