ec5f908775
Right now the riscv kernel has (at least) two independent sets of functions to check if an encoded instruction is of a specific type. One in kgdb and one kprobes simulate-insn code. More parts of the kernel will probably need this in the future, so instead of allowing this duplication to go on further, move macros that do the function declaration in a common header, similar to at least aarch64. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Link: https://lore.kernel.org/r/20221223221332.4127602-7-heiko@sntech.de Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
32 lines
948 B
C
32 lines
948 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _RISCV_KERNEL_PROBES_SIMULATE_INSN_H
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#define _RISCV_KERNEL_PROBES_SIMULATE_INSN_H
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#include <asm/parse_asm.h>
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#define RISCV_INSN_REJECTED(name, code) \
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do { \
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if (riscv_insn_is_##name(code)) { \
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return INSN_REJECTED; \
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} \
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} while (0)
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__RISCV_INSN_FUNCS(system, 0x7f, 0x73);
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__RISCV_INSN_FUNCS(fence, 0x7f, 0x0f);
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#define RISCV_INSN_SET_SIMULATE(name, code) \
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do { \
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if (riscv_insn_is_##name(code)) { \
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api->handler = simulate_##name; \
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return INSN_GOOD_NO_SLOT; \
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} \
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} while (0)
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bool simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs);
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bool simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs);
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bool simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs);
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bool simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);
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#endif /* _RISCV_KERNEL_PROBES_SIMULATE_INSN_H */
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