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Stephane Eranian 6d7a4a140c perf/x86/intel/ds: Fix precise store latency handling

commit d4bdb0bebc5ba3299d74f123c782d99cd4e25c49 upstream.

With the existing code in store_latency_data(), the memory operation (mem_op)
returned to the user is always OP_LOAD where in fact, it should be OP_STORE.
This comes from the fact that the function is simply grabbing the information
from a data source map which covers only load accesses. Intel 12th gen CPU
offers precise store sampling that captures both the data source and latency.
Therefore it can use the data source mapping table but must override the
memory operation to reflect stores instead of loads.

Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20220818054613.1548130-1-eranian@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2022-08-31 17:18:19 +02:00

alpha

Cleanups (and one fix) around struct mount handling.

2022-06-04 19:00:05 -07:00

arc

This set of changes updates init and user mode helper tasks to be

2022-06-03 16:03:05 -07:00

arm

ARM: Marvell: Update PCIe fixup

2022-08-17 15:16:09 +02:00

arm64

arm64: Fix match_list for erratum 1286807 on Arm Cortex-A76