Emil Renner Berthing ec85362fb1 RISC-V: Add initial StarFive JH7100 device tree ...

Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This
is a test chip for their upcoming JH7110 SoC.

The CPU and cache data is based on the device tree in the vendor u-boot
port.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>

2021-12-16 17:24:23 +01:00

..

dts

RISC-V: Add initial StarFive JH7100 device tree

2021-12-16 17:24:23 +01:00

.gitignore

riscv: Ignore Image.* and loader.bin

2020-11-09 11:54:46 -08:00

install.sh

…

loader.lds.S

riscv: Move kernel mapping outside of linear mapping

2021-04-26 08:25:04 -07:00

loader.S

riscv: provide a flat image loader

2019-11-17 15:17:39 -08:00

Makefile

riscv: move the (z)install rules to arch/riscv/Makefile

2021-09-10 23:08:26 -07:00