Swapnil Jakhade ede775a87b phy: cadence-torrent: Add PCIe + DP multilink configuration for 100MHz refclk
Add multilink DP configuration support for 100MHz reference clock rate.
This is the only clock rate supported currently for multilink PHY
configurations. Also, add PCIe + DP multiprotocol multilink register
configuration sequences for 100MHz refclk with no SSC.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20230418173157.25607-4-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-08 17:07:01 +05:30
..
2023-05-03 11:17:34 -07:00
2022-10-07 16:03:01 -07:00
2023-02-14 19:25:45 +05:30