783abfa224
Enable coresight support by adding device nodes for the available source, sinks and channel blocks on MSM8998. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
1831 lines
37 KiB
Plaintext
1831 lines
37 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8998.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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interrupt-parent = <&intc>;
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qcom,msm-id = <292 0x0>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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memory {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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memory@85800000 {
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reg = <0x0 0x85800000 0x0 0x800000>;
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no-map;
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};
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smem_mem: smem-mem@86000000 {
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reg = <0x0 0x86000000 0x0 0x200000>;
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no-map;
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};
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memory@86200000 {
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reg = <0x0 0x86200000 0x0 0x2d00000>;
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no-map;
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};
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rmtfs {
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compatible = "qcom,rmtfs-mem";
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size = <0x0 0x200000>;
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alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
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no-map;
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qcom,client-id = <1>;
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qcom,vmid = <15>;
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};
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};
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clocks {
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xo: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "xo_board";
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};
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sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32764>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
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next-level-cache = <&L2_0>;
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L1_I_1: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_1: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
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next-level-cache = <&L2_0>;
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L1_I_2: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_2: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
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next-level-cache = <&L2_0>;
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L1_I_3: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_3: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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L1_I_100: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_100: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
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next-level-cache = <&L2_1>;
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L1_I_101: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_101: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x102>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
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next-level-cache = <&L2_1>;
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L1_I_102: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_102: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x103>;
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enable-method = "psci";
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cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
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next-level-cache = <&L2_1>;
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L1_I_103: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_103: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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idle-state-name = "little-retention";
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arm,psci-suspend-param = <0x00000002>;
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entry-latency-us = <81>;
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exit-latency-us = <86>;
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min-residency-us = <200>;
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};
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LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
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compatible = "arm,idle-state";
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idle-state-name = "little-power-collapse";
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arm,psci-suspend-param = <0x40000003>;
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entry-latency-us = <273>;
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exit-latency-us = <612>;
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min-residency-us = <1000>;
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local-timer-stop;
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};
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BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
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compatible = "arm,idle-state";
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idle-state-name = "big-retention";
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arm,psci-suspend-param = <0x00000002>;
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entry-latency-us = <79>;
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exit-latency-us = <82>;
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min-residency-us = <200>;
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};
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BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
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compatible = "arm,idle-state";
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idle-state-name = "big-power-collapse";
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arm,psci-suspend-param = <0x40000003>;
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entry-latency-us = <336>;
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exit-latency-us = <525>;
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min-residency-us = <1000>;
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local-timer-stop;
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};
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-msm8998", "qcom,scm";
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};
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_regs 0 0x1000>;
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#hwlock-cells = <1>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&apcs_glb 0>;
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rpm_requests: rpm-requests {
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compatible = "qcom,rpm-msm8998";
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qcom,glink-channels = "rpm_requests";
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rpmcc: clock-controller {
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compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
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#clock-cells = <1>;
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};
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rpmpd: power-controller {
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compatible = "qcom,msm8998-rpmpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmpd_opp_table>;
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rpmpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmpd_opp_ret: opp1 {
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opp-level = <16>;
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};
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rpmpd_opp_ret_plus: opp2 {
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opp-level = <32>;
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};
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rpmpd_opp_min_svs: opp3 {
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opp-level = <48>;
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};
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rpmpd_opp_low_svs: opp4 {
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opp-level = <64>;
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};
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rpmpd_opp_svs: opp5 {
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opp-level = <128>;
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};
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rpmpd_opp_svs_plus: opp6 {
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opp-level = <192>;
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};
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rpmpd_opp_nom: opp7 {
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opp-level = <256>;
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};
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rpmpd_opp_nom_plus: opp8 {
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opp-level = <320>;
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};
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rpmpd_opp_turbo: opp9 {
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opp-level = <384>;
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};
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rpmpd_opp_turbo_plus: opp10 {
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opp-level = <512>;
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};
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};
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};
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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smp2p-lpass {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apcs_glb 10>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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adsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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adsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-mpss {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apcs_glb 14>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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modem_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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modem_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-slpi {
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compatible = "qcom,smp2p";
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qcom,smem = <481>, <430>;
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interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apcs_glb 26>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <3>;
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slpi_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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slpi_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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thermal-zones {
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cpu0-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 1>;
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trips {
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cpu0_alert0: trip-point@0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu0_crit: cpu_crit {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu1-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 2>;
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trips {
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cpu1_alert0: trip-point@0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu1_crit: cpu_crit {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu2-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 3>;
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trips {
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cpu2_alert0: trip-point@0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu2_crit: cpu_crit {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu3-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 4>;
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trips {
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cpu3_alert0: trip-point@0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu3_crit: cpu_crit {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu4-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 7>;
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trips {
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cpu4_alert0: trip-point@0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu4_crit: cpu_crit {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu5-thermal {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 8>;
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trips {
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cpu5_alert0: trip-point@0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu5_crit: cpu_crit {
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temperature = <110000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu6-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 9>;
|
|
|
|
trips {
|
|
cpu6_alert0: trip-point@0 {
|
|
temperature = <75000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu6_crit: cpu_crit {
|
|
temperature = <110000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu7-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 10>;
|
|
|
|
trips {
|
|
cpu7_alert0: trip-point@0 {
|
|
temperature = <75000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu7_crit: cpu_crit {
|
|
temperature = <110000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu-thermal-bottom {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 12>;
|
|
|
|
trips {
|
|
gpu1_alert0: trip-point@0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu-thermal-top {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 13>;
|
|
|
|
trips {
|
|
gpu2_alert0: trip-point@0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
clust0-mhm-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 5>;
|
|
|
|
trips {
|
|
cluster0_mhm_alert0: trip-point@0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
clust1-mhm-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 6>;
|
|
|
|
trips {
|
|
cluster1_mhm_alert0: trip-point@0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
cluster1-l2-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens0 11>;
|
|
|
|
trips {
|
|
cluster1_l2_alert0: trip-point@0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 1>;
|
|
|
|
trips {
|
|
modem_alert0: trip-point@0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
mem-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 2>;
|
|
|
|
trips {
|
|
mem_alert0: trip-point@0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
wlan-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 3>;
|
|
|
|
trips {
|
|
wlan_alert0: trip-point@0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
q6-dsp-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 4>;
|
|
|
|
trips {
|
|
q6_dsp_alert0: trip-point@0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
camera-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 5>;
|
|
|
|
trips {
|
|
camera_alert0: trip-point@0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
multimedia-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
|
|
thermal-sensors = <&tsens1 6>;
|
|
|
|
trips {
|
|
multimedia_alert0: trip-point@0 {
|
|
temperature = <90000>;
|
|
hysteresis = <2000>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
soc: soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,gcc-msm8998";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
reg = <0x00100000 0xb0000>;
|
|
};
|
|
|
|
rpm_msg_ram: memory@778000 {
|
|
compatible = "qcom,rpm-msg-ram";
|
|
reg = <0x00778000 0x7000>;
|
|
};
|
|
|
|
qfprom: qfprom@780000 {
|
|
compatible = "qcom,qfprom";
|
|
reg = <0x00780000 0x621c>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
qusb2_hstx_trim: hstx-trim@423a {
|
|
reg = <0x423a 0x1>;
|
|
bits = <0 4>;
|
|
};
|
|
};
|
|
|
|
tsens0: thermal@10ab000 {
|
|
compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
|
|
reg = <0x010ab000 0x1000>, /* TM */
|
|
<0x010aa000 0x1000>; /* SROT */
|
|
|
|
#qcom,sensors = <14>;
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens1: thermal@10ae000 {
|
|
compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
|
|
reg = <0x010ae000 0x1000>, /* TM */
|
|
<0x010ad000 0x1000>; /* SROT */
|
|
|
|
#qcom,sensors = <8>;
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
anoc1_smmu: iommu@1680000 {
|
|
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
|
|
reg = <0x01680000 0x10000>;
|
|
#iommu-cells = <1>;
|
|
|
|
#global-interrupts = <0>;
|
|
interrupts =
|
|
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
pcie0: pci@1c00000 {
|
|
compatible = "qcom,pcie-msm8996";
|
|
reg = <0x01c00000 0x2000>,
|
|
<0x1b000000 0xf1d>,
|
|
<0x1b000f20 0xa8>,
|
|
<0x1b100000 0x100000>;
|
|
reg-names = "parf", "dbi", "elbi", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
bus-range = <0x00 0xff>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
num-lanes = <1>;
|
|
phys = <&pciephy>;
|
|
phy-names = "pciephy";
|
|
|
|
ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
|
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_0_AUX_CLK>;
|
|
clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
|
|
|
|
power-domains = <&gcc PCIE_0_GDSC>;
|
|
iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
|
|
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
phy@1c06000 {
|
|
compatible = "qcom,msm8998-qmp-pcie-phy";
|
|
reg = <0x01c06000 0x18c>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_CLKREF_CLK>;
|
|
clock-names = "aux", "cfg_ahb", "ref";
|
|
|
|
resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
|
|
reset-names = "phy", "common";
|
|
|
|
vdda-phy-supply = <&vreg_l1a_0p875>;
|
|
vdda-pll-supply = <&vreg_l2a_1p2>;
|
|
|
|
pciephy: lane@1c06800 {
|
|
reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
|
|
clock-names = "pipe0";
|
|
clock-output-names = "pcie_0_pipe_clk_src";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
ufshc: ufshc@1da4000 {
|
|
compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
|
|
reg = <0x01da4000 0x2500>;
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufsphy_lanes>;
|
|
phy-names = "ufsphy";
|
|
lanes-per-direction = <2>;
|
|
power-domains = <&gcc UFS_GDSC>;
|
|
#reset-cells = <1>;
|
|
|
|
clock-names =
|
|
"core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk",
|
|
"rx_lane1_sync_clk";
|
|
clocks =
|
|
<&gcc GCC_UFS_AXI_CLK>,
|
|
<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
|
|
<&gcc GCC_UFS_AHB_CLK>,
|
|
<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
|
|
<&rpmcc RPM_SMD_LN_BB_CLK1>,
|
|
<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
|
|
freq-table-hz =
|
|
<50000000 200000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<37500000 150000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
|
|
resets = <&gcc GCC_UFS_BCR>;
|
|
reset-names = "rst";
|
|
};
|
|
|
|
ufsphy: phy@1da7000 {
|
|
compatible = "qcom,msm8998-qmp-ufs-phy";
|
|
reg = <0x01da7000 0x18c>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
clock-names =
|
|
"ref",
|
|
"ref_aux";
|
|
clocks =
|
|
<&gcc GCC_UFS_CLKREF_CLK>,
|
|
<&gcc GCC_UFS_PHY_AUX_CLK>;
|
|
|
|
reset-names = "ufsphy";
|
|
resets = <&ufshc 0>;
|
|
|
|
ufsphy_lanes: lanes@1da7400 {
|
|
reg = <0x01da7400 0x128>,
|
|
<0x01da7600 0x1fc>,
|
|
<0x01da7c00 0x1dc>,
|
|
<0x01da7800 0x128>,
|
|
<0x01da7a00 0x1fc>;
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
|
|
tcsr_mutex_regs: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x01f40000 0x20000>;
|
|
};
|
|
|
|
tlmm: pinctrl@3400000 {
|
|
compatible = "qcom,msm8998-pinctrl";
|
|
reg = <0x03400000 0xc00000>;
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
stm@6002000 {
|
|
compatible = "arm,coresight-stm", "arm,primecell";
|
|
reg = <0x06002000 0x1000>,
|
|
<0x16280000 0x180000>;
|
|
reg-names = "stm-base", "stm-data-base";
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
out-ports {
|
|
port {
|
|
stm_out: endpoint {
|
|
remote-endpoint = <&funnel0_in7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6041000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x06041000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
out-ports {
|
|
port {
|
|
funnel0_out: endpoint {
|
|
remote-endpoint =
|
|
<&merge_funnel_in0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
funnel0_in7: endpoint {
|
|
remote-endpoint = <&stm_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6042000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x06042000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
out-ports {
|
|
port {
|
|
funnel1_out: endpoint {
|
|
remote-endpoint =
|
|
<&merge_funnel_in1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
funnel1_in6: endpoint {
|
|
remote-endpoint =
|
|
<&apss_merge_funnel_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@6045000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x06045000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
out-ports {
|
|
port {
|
|
merge_funnel_out: endpoint {
|
|
remote-endpoint =
|
|
<&etf_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
merge_funnel_in0: endpoint {
|
|
remote-endpoint =
|
|
<&funnel0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
merge_funnel_in1: endpoint {
|
|
remote-endpoint =
|
|
<&funnel1_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@6046000 {
|
|
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
|
reg = <0x06046000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
out-ports {
|
|
port {
|
|
replicator_out: endpoint {
|
|
remote-endpoint = <&etr_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
port {
|
|
replicator_in: endpoint {
|
|
remote-endpoint = <&etf_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etf@6047000 {
|
|
compatible = "arm,coresight-tmc", "arm,primecell";
|
|
reg = <0x06047000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
out-ports {
|
|
port {
|
|
etf_out: endpoint {
|
|
remote-endpoint =
|
|
<&replicator_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
port {
|
|
etf_in: endpoint {
|
|
remote-endpoint =
|
|
<&merge_funnel_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etr@6048000 {
|
|
compatible = "arm,coresight-tmc", "arm,primecell";
|
|
reg = <0x06048000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
arm,scatter-gather;
|
|
|
|
in-ports {
|
|
port {
|
|
etr_in: endpoint {
|
|
remote-endpoint =
|
|
<&replicator_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7840000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x07840000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
cpu = <&CPU0>;
|
|
|
|
out-ports {
|
|
port {
|
|
etm0_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel_in0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7940000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x07940000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
cpu = <&CPU1>;
|
|
|
|
out-ports {
|
|
port {
|
|
etm1_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel_in1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7a40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x07a40000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
cpu = <&CPU2>;
|
|
|
|
out-ports {
|
|
port {
|
|
etm2_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel_in2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7b40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x07b40000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
cpu = <&CPU3>;
|
|
|
|
out-ports {
|
|
port {
|
|
etm3_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel_in3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@7b60000 { /* APSS Funnel */
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x07b60000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
out-ports {
|
|
port {
|
|
apss_funnel_out: endpoint {
|
|
remote-endpoint =
|
|
<&apss_merge_funnel_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
apss_funnel_in0: endpoint {
|
|
remote-endpoint =
|
|
<&etm0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
apss_funnel_in1: endpoint {
|
|
remote-endpoint =
|
|
<&etm1_out>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
apss_funnel_in2: endpoint {
|
|
remote-endpoint =
|
|
<&etm2_out>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
apss_funnel_in3: endpoint {
|
|
remote-endpoint =
|
|
<&etm3_out>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
apss_funnel_in4: endpoint {
|
|
remote-endpoint =
|
|
<&etm4_out>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
apss_funnel_in5: endpoint {
|
|
remote-endpoint =
|
|
<&etm5_out>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
apss_funnel_in6: endpoint {
|
|
remote-endpoint =
|
|
<&etm6_out>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <7>;
|
|
apss_funnel_in7: endpoint {
|
|
remote-endpoint =
|
|
<&etm7_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@7b70000 {
|
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
|
reg = <0x07b70000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
out-ports {
|
|
port {
|
|
apss_merge_funnel_out: endpoint {
|
|
remote-endpoint =
|
|
<&funnel1_in6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
port {
|
|
apss_merge_funnel_in: endpoint {
|
|
remote-endpoint =
|
|
<&apss_funnel_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7c40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x07c40000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
cpu = <&CPU4>;
|
|
|
|
port{
|
|
etm4_out: endpoint {
|
|
remote-endpoint = <&apss_funnel_in4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7d40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x07d40000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
cpu = <&CPU5>;
|
|
|
|
port{
|
|
etm5_out: endpoint {
|
|
remote-endpoint = <&apss_funnel_in5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7e40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x07e40000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
cpu = <&CPU6>;
|
|
|
|
port{
|
|
etm6_out: endpoint {
|
|
remote-endpoint = <&apss_funnel_in6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@7f40000 {
|
|
compatible = "arm,coresight-etm4x", "arm,primecell";
|
|
reg = <0x07f40000 0x1000>;
|
|
|
|
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
|
|
clock-names = "apb_pclk", "atclk";
|
|
|
|
cpu = <&CPU7>;
|
|
|
|
port{
|
|
etm7_out: endpoint {
|
|
remote-endpoint = <&apss_funnel_in7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
spmi_bus: spmi@800f000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x0800f000 0x1000>,
|
|
<0x08400000 0x1000000>,
|
|
<0x09400000 0x1000000>,
|
|
<0x0a400000 0x220000>,
|
|
<0x0800a000 0x3000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
cell-index = <0>;
|
|
};
|
|
|
|
usb3: usb@a8f8800 {
|
|
compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
|
|
reg = <0x0a8f8800 0x400>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
|
|
<&gcc GCC_USB30_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE1_USB3_AXI_CLK>,
|
|
<&gcc GCC_USB30_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_SLEEP_CLK>;
|
|
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
|
|
"sleep";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <120000000>;
|
|
|
|
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hs_phy_irq", "ss_phy_irq";
|
|
|
|
power-domains = <&gcc USB_30_GDSC>;
|
|
|
|
resets = <&gcc GCC_USB_30_BCR>;
|
|
|
|
usb3_dwc3: dwc3@a800000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0a800000 0xcd00>;
|
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
phys = <&qusb2phy>, <&usb1_ssphy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
snps,has-lpm-erratum;
|
|
snps,hird-threshold = /bits/ 8 <0x10>;
|
|
};
|
|
};
|
|
|
|
usb3phy: phy@c010000 {
|
|
compatible = "qcom,msm8998-qmp-usb3-phy";
|
|
reg = <0x0c010000 0x18c>;
|
|
status = "disabled";
|
|
#clock-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
|
|
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
|
|
<&gcc GCC_USB3_CLKREF_CLK>;
|
|
clock-names = "aux", "cfg_ahb", "ref";
|
|
|
|
resets = <&gcc GCC_USB3_PHY_BCR>,
|
|
<&gcc GCC_USB3PHY_PHY_BCR>;
|
|
reset-names = "phy", "common";
|
|
|
|
usb1_ssphy: lane@c010200 {
|
|
reg = <0xc010200 0x128>,
|
|
<0xc010400 0x200>,
|
|
<0xc010c00 0x20c>,
|
|
<0xc010600 0x128>,
|
|
<0xc010800 0x200>;
|
|
#phy-cells = <0>;
|
|
clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
|
|
clock-names = "pipe0";
|
|
clock-output-names = "usb3_phy_pipe_clk_src";
|
|
};
|
|
};
|
|
|
|
qusb2phy: phy@c012000 {
|
|
compatible = "qcom,msm8998-qusb2-phy";
|
|
reg = <0x0c012000 0x2a8>;
|
|
status = "disabled";
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
|
|
<&gcc GCC_RX1_USB2_CLKREF_CLK>;
|
|
clock-names = "cfg_ahb", "ref";
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
|
|
|
nvmem-cells = <&qusb2_hstx_trim>;
|
|
};
|
|
|
|
sdhc2: sdhci@c0a4900 {
|
|
compatible = "qcom,sdhci-msm-v4";
|
|
reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
|
|
reg-names = "hc_mem", "core_mem";
|
|
|
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
clock-names = "iface", "core", "xo";
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>,
|
|
<&xo>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c1: i2c@c175000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c175000 0x600>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
blsp1_i2c2: i2c@c176000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c176000 0x600>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
blsp1_i2c3: i2c@c177000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c177000 0x600>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
blsp1_i2c4: i2c@c178000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c178000 0x600>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
blsp1_i2c5: i2c@c179000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c179000 0x600>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
blsp1_i2c6: i2c@c17a000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c17a000 0x600>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
blsp2_uart1: serial@c1b0000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x0c1b0000 0x1000>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp2_i2c0: i2c@c1b5000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c1b5000 0x600>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
blsp2_i2c1: i2c@c1b6000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c1b6000 0x600>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
blsp2_i2c2: i2c@c1b7000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c1b7000 0x600>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
blsp2_i2c3: i2c@c1b8000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c1b8000 0x600>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
blsp2_i2c4: i2c@c1b9000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c1b9000 0x600>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
blsp2_i2c5: i2c@c1ba000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0x0c1ba000 0x600>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
apcs_glb: mailbox@17911000 {
|
|
compatible = "qcom,msm8998-apcs-hmss-global";
|
|
reg = <0x17911000 0x1000>;
|
|
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
timer@17920000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17920000 0x1000>;
|
|
|
|
frame@17921000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17921000 0x1000>,
|
|
<0x17922000 0x1000>;
|
|
};
|
|
|
|
frame@17923000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17923000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17924000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17924000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17925000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17925000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17926000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17926000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17927000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17927000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17928000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17928000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x17a00000 0x10000>, /* GICD */
|
|
<0x17b00000 0x100000>; /* GICR * 8 */
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "msm8998-pins.dtsi"
|