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Arnd Bergmann ee7dad0b81 RISC-V Devicetrees for v6.9

Microchip:
 Missing bus clocks for the CAN controllers spotted during the creation
 of a driver for the controllers and a specific compatible for the SiFive
 PDMA block on PolarFire SoC.
 
 Starfive:
 PWM nodes for the jh7100 and jh7110. Camera subsystem support for the
 latter. Most notably however is the addition of ethernet support for the
 jh7110 which finally allows people to use the network on the OG VisionFive
 and on the Beagle-V Starlight board. This was made possible by the
 non-standard cache management operations support added for the RZ/Five
 which could be extended to the ccache present on the jh7100.
 
 bindings:
 Additional clarification for what the reg property represents for cpus
 and two opencores PWM binding changes - the original addition and an
 added compatible. The latter is here as the driver patch was not ready
 but the PWM maintainer told me to go ahead and merge it.
 
 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Merge tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/late

RISC-V Devicetrees for v6.9

Microchip:
Missing bus clocks for the CAN controllers spotted during the creation
of a driver for the controllers and a specific compatible for the SiFive
PDMA block on PolarFire SoC.

Starfive:
PWM nodes for the jh7100 and jh7110. Camera subsystem support for the
latter. Most notably however is the addition of ethernet support for the
jh7110 which finally allows people to use the network on the OG VisionFive
and on the Beagle-V Starlight board. This was made possible by the
non-standard cache management operations support added for the RZ/Five
which could be extended to the ccache present on the jh7100.

bindings:
Additional clarification for what the reg property represents for cpus
and two opencores PWM binding changes - the original addition and an
added compatible. The latter is here as the driver patch was not ready
but the PWM maintainer told me to go ahead and merge it.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: jh7110: Add camera subsystem nodes
  dt-bindings: pwm: opencores: Add compatible for StarFive JH8100
  dt-bindings: riscv: cpus: reg matches hart ID
  riscv: dts: microchip: add specific compatible for mpfs pdma
  riscv: dts: microchip: add missing CAN bus clocks
  riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio
  riscv: dts: starfive: visionfive-v1: Setup ethernet phy
  riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac
  riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes
  riscv: dts: starfive: jh7110: Add PWM node and pins configuration
  riscv: dts: starfive: jh7100: Add PWM node and pins configuration
  dt-bindings: pwm: Add bindings for OpenCores PWM Controller

Link: https://lore.kernel.org/r/20240305-iodine-moneywise-53797ae9bf6e@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

2024-03-06 07:40:29 +01:00

alpha

RTC for 6.8

2024-01-18 17:25:39 -08:00

arc

work around gcc bugs with 'asm goto' with outputs

2024-02-09 15:57:48 -08:00

arm

Update TI clksel clocks to use reg

2024-03-04 17:37:02 +01:00

arm64

Arm and RISC-V SoC fixes for 6.8, part 2