Conor Dooley efa310ba00 riscv: dts: microchip: hook up the mpfs' l2cache ... The initial PolarFire SoC devicetree must have been forked off from the fu540 one prior to the addition of l2cache controller support being added there. When the controller node was added to mpfs.dtsi, it was not hooked up to the CPUs & thus sysfs reports an incorrect cache configuration. Hook it up. Fixes: 0fa6107eca ("RISC-V: Initial DTS for Microchip ICICLE board") Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2022-07-05 16:54:03 +01:00
..
boot	riscv: dts: microchip: hook up the mpfs' l2cache	2022-07-05 16:54:03 +01:00
configs	RISC-V: configs: Configs that had RPMSG_CHAR now get RPMSG_CTRL	2022-04-26 08:19:53 -07:00
errata	riscv: add memory-type errata for T-Head	2022-05-11 21:36:33 -07:00
include	riscv: Move alternative length validation into subsection	2022-06-02 15:55:22 -07:00
kernel	Bitmap patches for 5.19-rc1	2022-06-04 14:04:27 -07:00
kvm	RISC-V: KVM: Introduce ISA extension register	2022-05-20 09:09:20 +05:30
lib	riscv: Fixed misaligned memory access. Fixed pointer comparison.	2022-03-10 10:24:04 -08:00
mm	riscv: mm: init: make pt_ops_set_[early|late|fixmap] static	2022-06-02 14:50:41 -07:00
net	riscv, bpf: Implement more atomic operations for RV64	2022-04-11 16:54:54 +02:00
purgatory	RISC-V: Add purgatory	2022-05-19 12:18:59 -07:00
Kbuild	riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild	2022-06-01 22:26:32 -07:00
Kconfig	RISC-V: Only default to spinwait on SBI-0.1 and M-mode	2022-06-01 18:59:26 -07:00
Kconfig.debug
Kconfig.erratas	riscv: add memory-type errata for T-Head	2022-05-11 21:36:33 -07:00
Kconfig.socs	RISC-V Patches for the 5.19 Merge Window, Part 1	2022-05-31 14:10:54 -07:00
Makefile	riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild	2022-06-01 22:26:32 -07:00