d0e3d29f87
Add the compatible for the MAC controller on sa8775p platforms. This MAC works with a single interrupt so add minItems to the interrupts property. The fourth clock's name is different here so change it. Enable relevant PHY properties. Add the relevant compatibles to the binding document for snps,dwmac as well. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
122 lines
2.6 KiB
YAML
122 lines
2.6 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/qcom,ethqos.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Ethernet ETHQOS device
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maintainers:
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- Bhupesh Sharma <bhupesh.sharma@linaro.org>
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description:
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dwmmac based Qualcomm ethernet devices which support Gigabit
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ethernet (version v2.3.0 and onwards).
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allOf:
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- $ref: snps,dwmac.yaml#
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properties:
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compatible:
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enum:
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- qcom,qcs404-ethqos
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- qcom,sa8775p-ethqos
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- qcom,sc8280xp-ethqos
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- qcom,sm8150-ethqos
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: stmmaceth
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- const: rgmii
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interrupts:
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minItems: 1
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items:
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- description: Combined signal for various interrupt events
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- description: The interrupt that occurs when Rx exits the LPI state
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interrupt-names:
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minItems: 1
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items:
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- const: macirq
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- const: eth_lpi
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: stmmaceth
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- const: pclk
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- const: ptp_ref
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- enum:
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- rgmii
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- phyaux
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iommus:
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maxItems: 1
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phys: true
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phy-names:
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const: serdes
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required:
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- compatible
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- clocks
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- clock-names
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- reg-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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#include <dt-bindings/gpio/gpio.h>
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ethernet: ethernet@7a80000 {
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compatible = "qcom,qcs404-ethqos";
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reg = <0x07a80000 0x10000>,
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<0x07a96000 0x100>;
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reg-names = "stmmaceth", "rgmii";
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clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
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clocks = <&gcc GCC_ETH_AXI_CLK>,
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<&gcc GCC_ETH_SLAVE_AHB_CLK>,
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<&gcc GCC_ETH_PTP_CLK>,
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<&gcc GCC_ETH_RGMII_CLK>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq", "eth_lpi";
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rx-fifo-depth = <4096>;
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tx-fifo-depth = <4096>;
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snps,tso;
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snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 10000>;
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pinctrl-names = "default";
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pinctrl-0 = <ðernet_defaults>;
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phy-handle = <&phy1>;
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phy-mode = "rgmii";
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mdio {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "snps,dwmac-mdio";
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phy1: phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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device_type = "ethernet-phy";
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reg = <0x4>;
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#phy-cells = <0>;
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};
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};
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};
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