Sohil Mehta f1ac10c24e iommu/vt-d: Add a check for 5-level paging support
Add a check to verify IOMMU 5-level paging support. If the CPU supports
supports 5-level paging but the IOMMU does not support it then disable
SVM by not allocating PASID tables.

Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2018-01-17 15:02:50 +01:00
..
2017-09-09 15:03:24 -07:00
2017-11-14 16:43:27 -08:00
2017-08-23 16:28:09 +02:00
2017-08-10 00:03:50 +02:00
2017-11-06 10:40:53 -07:00