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Atish Patra f1e58583b9
RISC-V: Support cpu hotplug 
This patch enable support for cpu hotplug in RISC-V. It uses SBI HSM
extension to online/offline any hart. As a result, the harts are
returned to firmware once they are offline. If the harts are brought
online afterwards, they re-enter Linux kernel as if a secondary hart
booted for the first time. All booting requirements are honored during
this process.

Tested both on QEMU and HighFive Unleashed board with. Test result follows.

---------------------------------------------------
Offline cpu 2
---------------------------------------------------
$ echo 0 > /sys/devices/system/cpu/cpu2/online
[   32.828684] CPU2: off
$ cat /proc/cpuinfo
processor       : 0
hart            : 0
isa             : rv64imafdcsu
mmu             : sv48

processor       : 1
hart            : 1
isa             : rv64imafdcsu
mmu             : sv48

processor       : 3
hart            : 3
isa             : rv64imafdcsu
mmu             : sv48

processor       : 4
hart            : 4
isa             : rv64imafdcsu
mmu             : sv48

processor       : 5
hart            : 5
isa             : rv64imafdcsu
mmu             : sv48

processor       : 6
hart            : 6
isa             : rv64imafdcsu
mmu             : sv48

processor       : 7
hart            : 7
isa             : rv64imafdcsu
mmu             : sv48

---------------------------------------------------
online cpu 2
---------------------------------------------------
$ echo 1 > /sys/devices/system/cpu/cpu2/online
$ cat /proc/cpuinfo
processor       : 0
hart            : 0
isa             : rv64imafdcsu
mmu             : sv48

processor       : 1
hart            : 1
isa             : rv64imafdcsu
mmu             : sv48

processor       : 2
hart            : 2
isa             : rv64imafdcsu
mmu             : sv48

processor       : 3
hart            : 3
isa             : rv64imafdcsu
mmu             : sv48

processor       : 4
hart            : 4
isa             : rv64imafdcsu
mmu             : sv48

processor       : 5
hart            : 5
isa             : rv64imafdcsu
mmu             : sv48

processor       : 6
hart            : 6
isa             : rv64imafdcsu
mmu             : sv48

processor       : 7
hart            : 7
isa             : rv64imafdcsu
mmu             : sv48

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2020-03-31 11:28:30 -07:00
..
asm-offsets.h
…
asm-prototypes.h
riscv: Less inefficient gcc tishift helpers (and export their symbols)
2020-01-18 19:13:41 -08:00
asm.h
RISC-V: Clear load reservations while restoring hart contexts
2019-10-01 13:16:40 -07:00
atomic.h
locking/atomic, riscv: Use s64 for atomic64
2019-06-03 12:32:56 +02:00
barrier.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234
2019-06-19 17:09:07 +02:00
bitops.h
RISC-V patches for v5.2-rc6
2019-06-17 10:34:03 -07:00
bug.h
riscv: add macro to get instruction length
2020-03-26 09:24:49 -07:00
cache.h
riscv: add nommu support
2019-11-17 15:17:39 -08:00
cacheflush.h
riscv: Use flush_icache_mm for flush_icache_user_range
2020-03-03 10:28:10 -08:00
clint.h
riscv: provide native clint access for M-mode
2019-11-17 15:17:39 -08:00
cmpxchg.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
cpu_ops.h
RISC-V: Support cpu hotplug
2020-03-31 11:28:30 -07:00
csr.h
riscv: set pmp configuration if kernel is running in M-mode
2020-02-18 09:41:24 -08:00
current.h
RISC-V: Stop relying on GCC's register allocator's hueristics
2020-03-03 10:28:13 -08:00
delay.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
elf.h
riscv: add nommu support
2019-11-17 15:17:39 -08:00
fence.h
riscv/spinlock: Strengthen implementations with fences
2018-04-02 19:59:43 -07:00
fixmap.h
riscv: introduce interfaces to patch kernel code
2020-03-26 09:24:52 -07:00
ftrace.h
riscv: clean up the macro format in each header file
2019-11-12 12:04:52 -08:00
futex.h
Merge branch 'next/nommu' into for-next
2019-11-22 18:59:09 -08:00
hugetlb.h
riscv: Introduce huge page support for 32/64bit kernel
2019-07-03 15:23:38 -07:00
hwcap.h
riscv: clean up the macro format in each header file
2019-11-12 12:04:52 -08:00
image.h
RISC-V: Typo fixes in image header and documentation.
2019-12-19 09:32:45 -07:00
io.h
riscv: add nommu support
2019-11-17 15:17:39 -08:00
irq.h
riscv: add missing header file includes
2019-10-28 00:46:01 -07:00
irqflags.h
riscv: abstract out CSR names for supervisor vs machine mode
2019-11-05 09:20:42 -08:00
kasan.h
riscv: Use macro definition instead of magic number
2020-03-26 09:29:53 -07:00
Kbuild
asm-generic: Make dma-contiguous.h a mandatory include/asm header
2020-02-04 11:38:59 +01:00
kprobes.h
riscv: clean up the macro format in each header file
2019-11-12 12:04:52 -08:00
linkage.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
mmio.h
generic ioremap support
2019-11-28 10:57:12 -08:00
mmiowb.h
riscv: clean up the macro format in each header file
2019-11-12 12:04:52 -08:00
mmu_context.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
mmu.h
riscv: add nommu support
2019-11-17 15:17:39 -08:00
module.h
RISC-V: Support MODULE_SECTIONS mechanism on RV32
2019-01-07 08:19:20 -08:00
page.h
riscv: mm: add support for CONFIG_DEBUG_VIRTUAL
2020-01-23 10:40:06 -08:00
patch.h
riscv: introduce interfaces to patch kernel code
2020-03-26 09:24:52 -07:00
pci.h
riscv: clean up the macro format in each header file
2019-11-12 12:04:52 -08:00
perf_event.h
riscv, perf: Add arch specific perf_arch_bpf_user_pt_regs
2019-12-19 16:03:31 +01:00
pgalloc.h
riscv: add nommu support
2019-11-17 15:17:39 -08:00
pgtable-32.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
pgtable-64.h
riscv: mm: add p?d_leaf() definitions
2020-02-04 03:05:24 +00:00
pgtable-bits.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
pgtable.h
riscv: Add support to dump the kernel page tables
2020-03-26 09:29:49 -07:00
processor.h
riscv: abstract out CSR names for supervisor vs machine mode
2019-11-05 09:20:42 -08:00
ptdump.h
riscv: Add support to dump the kernel page tables
2020-03-26 09:29:49 -07:00
ptrace.h
riscv: abstract out CSR names for supervisor vs machine mode
2019-11-05 09:20:42 -08:00
sbi.h
RISC-V: Add SBI HSM extension definitions
2020-03-31 11:26:05 -07:00
seccomp.h
riscv: add support for SECCOMP and SECCOMP_FILTER
2019-10-29 11:32:10 -07:00
set_memory.h
riscv: add STRICT_KERNEL_RWX support
2020-03-26 09:24:45 -07:00
smp.h
RISC-V: Support cpu hotplug
2020-03-31 11:28:30 -07:00
sparsemem.h
riscv: clean up the macro format in each header file
2019-11-12 12:04:52 -08:00
spinlock_types.h
riscv: clean up the macro format in each header file
2019-11-12 12:04:52 -08:00
spinlock.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
string.h
riscv: Add KASAN support
2020-01-22 13:09:58 -08:00
switch_to.h
riscv: abstract out CSR names for supervisor vs machine mode
2019-11-05 09:20:42 -08:00
syscall.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
thread_info.h
riscv: add support for SECCOMP and SECCOMP_FILTER
2019-10-29 11:32:10 -07:00
timex.h
riscv: add support for MMIO access to the timer registers
2019-11-13 14:10:40 -08:00
tlb.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
tlbflush.h
riscv: add nommu support
2019-11-17 15:17:39 -08:00
uaccess.h
riscv: add nommu support
2019-11-17 15:17:39 -08:00
unistd.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
vdso.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234
2019-06-19 17:09:07 +02:00
vmalloc.h
mm/vmalloc: Add empty <asm/vmalloc.h> headers and use them from <linux/vmalloc.h>
2019-12-10 10:12:55 +01:00
word-at-a-time.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00