ae909ea4ad
Most of the more modern ColdFire cores use the same code to reset the CPU (but it is different to most of the earlier cores). Currently that is duplicated in each of the sub-arch files. Pull out this common code and out a single copy of it with the other common reset code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
67 lines
1.6 KiB
C
67 lines
1.6 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/523x/config.c
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*
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* Sub-architcture dependent initialization code for the Freescale
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* 523x CPUs.
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*
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* Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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/***************************************************************************/
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#ifdef CONFIG_SPI_COLDFIRE_QSPI
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static void __init m523x_qspi_init(void)
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{
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u16 par;
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/* setup QSPS pins for QSPI with gpio CS control */
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writeb(0x1f, MCFGPIO_PAR_QSPI);
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/* and CS2 & CS3 as gpio */
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par = readw(MCFGPIO_PAR_TIMER);
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par &= 0x3f3f;
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writew(par, MCFGPIO_PAR_TIMER);
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}
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#endif /* CONFIG_SPI_COLDFIRE_QSPI */
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/***************************************************************************/
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static void __init m523x_fec_init(void)
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{
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u16 par;
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u8 v;
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/* Set multi-function pins to ethernet use */
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par = readw(MCF_IPSBAR + 0x100082);
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writew(par | 0xf00, MCF_IPSBAR + 0x100082);
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v = readb(MCF_IPSBAR + 0x100078);
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writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_sched_init = hw_timer_init;
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m523x_fec_init();
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#ifdef CONFIG_SPI_COLDFIRE_QSPI
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m523x_qspi_init();
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#endif
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}
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/***************************************************************************/
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