Fahad Kunnathadi f2654a4781 net: phy: Fix mask value write on gmii2rgmii converter speed register
To clear Speed Selection in MDIO control register(0x10),
ie, clear bits 6 and 13 to zero while keeping other bits same.
Before AND operation,The Mask value has to be perform with bitwise NOT
operation (ie, ~ operator)

This patch clears current speed selection before writing the
new speed settings to gmii2rgmii converter

Fixes: f411a6160bd4 ("net: phy: Add gmiitorgmii converter support")

Signed-off-by: Fahad Kunnathadi <fahad.kunnathadi@dexceldesigns.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-09-18 16:33:18 -07:00
..
2017-05-30 12:42:27 -04:00
2017-03-24 15:33:32 +01:00
2017-08-06 20:55:28 -07:00
2017-08-06 20:55:28 -07:00