linux

iv/linux

History

Linus Torvalds c6cc9799b4 RISC-V Fixes for 6.10-rc2

* A fix to avoid pt_regs aliasing with idle thread stacks on secondary
   harts.
 * HAVE_ARCH_HUGE_VMAP is enabled on XIP kernels, which fixes boot issues
   on XIP systems with huge pages.
 * An update to the uABI documentation clarifying that only scalar
   misaligned accesses were grandfathered in as supported, as the vector
   extension did not exist at the time the uABI was frozen.
 * A fix for the recently-added byte/half atomics to avoid losing the
   fully ordered decorations.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmZZ9VkTHHBhbG1lckBk
 YWJiZWx0LmNvbQAKCRAuExnzX7sYiW5HD/93b41B8trlOWwDdLoMtHYT0qyPy6yC
 4YG20Yi0hXjLqw+6ZxmxUkUVwMU2T5l3RlIW9dsG0i/YXzAF73nNlOU62ihfMdyx
 /qG2zdo+Q/Z82ahQowgs4R+FaNUJrxGXrXFmO2A2PSZUb/SW7fzTUPzDQsSBlte9
 6SHpVXdaDSBkLLpH06Gy2IbQ2xtrBLEPxjjsK3YUIgW00a0VN3dw3MZzIAawYt1c
 dAF5yGLy8VP0ay/MTbdDHupV9EU74pdpyrCkOStjCrGYHiJ6WBGEbLsfi7OM1eRy
 KTJ/HuVeIm38vh+Q1LClm+vizr81FE7i/+x/3dQ+S0tw7+4O+BNbxKYeT0RqNHDF
 2JMup3EZulIJ2Ob4lBvamJP5Yid0VeChEiH43xm4TbJdUiAh9xS2RISru+dgxXhl
 nFHrqs/wwDxRmzaOB38nbq3OpkP2dEq+agON1dioH3OCWDLPrm6nUbl3bYR3IXSS
 LWbeBQOe4cImdVOt1QTF66he6PT/H7Ly9E+PxWHFjdFXwtZNF0xrjoAEyk4fj0Rf
 E17H2QdTLzqpdvu16OdxAtMFQiWjxsE/luwz2rYvfXvtPaIwcMu3oWuxZDRY8xCW
 i/snVIVdnHNaXnJRm9ttDLc0aX5Fuq7MMH8nqZH5RQnSUn7La9qBDoftjSoH4imL
 AccsI6pVOaipvg==
 =KSav
 -----END PGP SIGNATURE-----

Merge tag 'riscv-for-linus-6.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

 - A fix to avoid pt_regs aliasing with idle thread stacks on secondary
   harts.

 - HAVE_ARCH_HUGE_VMAP is enabled on XIP kernels, which fixes boot
   issues on XIP systems with huge pages.

 - An update to the uABI documentation clarifying that only scalar
   misaligned accesses were grandfathered in as supported, as the vector
   extension did not exist at the time the uABI was frozen.

 - A fix for the recently-added byte/half atomics to avoid losing the
   fully ordered decorations.

* tag 'riscv-for-linus-6.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Fix fully ordered LR/SC xchg[8|16]() implementations
  Documentation: RISC-V: uabi: Only scalar misaligned loads are supported
  riscv: enable HAVE_ARCH_HUGE_VMAP for XIP kernel
  riscv: prevent pt_regs corruption for secondary idle threads

2024-05-31 11:52:06 -07:00

alpha

mseal: wire up mseal syscall

2024-05-23 19:40:26 -07:00

arc

bpf-for-netdev

2024-05-27 16:26:30 -07:00

arm

mseal: wire up mseal syscall

2024-05-23 19:40:26 -07:00

arm64

16 hotfixes, 11 of which are cc:stable.