095730dd4c
i.MX MU has a MUR bit which is to reset both the Processor B and the Processor A sides of the MU module, forcing all control and status registers to return to their default values (except the BHR bit in the ACR register and BHRM bit in BCR register), and all internal states to be cleared. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
136 lines
3.4 KiB
YAML
136 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX Messaging Unit (MU)
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maintainers:
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- Dong Aisheng <aisheng.dong@nxp.com>
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description: |
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The Messaging Unit module enables two processors within the SoC to
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communicate and coordinate by passing messages (e.g. data, status
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and control) through the MU interface. The MU also provides the ability
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for one processor to signal the other processor using interrupts.
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Because the MU manages the messaging between processors, the MU uses
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different clocks (from each side of the different peripheral buses).
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Therefore, the MU must synchronize the accesses from one side to the
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other. The MU accomplishes synchronization using two sets of matching
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registers (Processor A-facing, Processor B-facing).
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properties:
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compatible:
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oneOf:
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- const: fsl,imx6sx-mu
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- const: fsl,imx7ulp-mu
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- const: fsl,imx8ulp-mu
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- const: fsl,imx8-mu-scu
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- const: fsl,imx8-mu-seco
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- const: fsl,imx93-mu-s4
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- const: fsl,imx8ulp-mu-s4
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- items:
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- const: fsl,imx93-mu
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- const: fsl,imx8ulp-mu
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- items:
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- enum:
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- fsl,imx7s-mu
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- fsl,imx8mq-mu
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- fsl,imx8mm-mu
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- fsl,imx8mn-mu
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- fsl,imx8mp-mu
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- fsl,imx8qm-mu
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- fsl,imx8qxp-mu
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- const: fsl,imx6sx-mu
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- description: To communicate with i.MX8 SCU with fast IPC
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items:
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- const: fsl,imx8-mu-scu
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- enum:
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- fsl,imx8qm-mu
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- fsl,imx8qxp-mu
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- const: fsl,imx6sx-mu
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 2
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interrupt-names:
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minItems: 1
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items:
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- const: tx
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- const: rx
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"#mbox-cells":
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description: |
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<&phandle type channel>
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phandle : Label name of controller
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type : Channel type
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channel : Channel number
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This MU support 5 type of unidirectional channels, each type
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has 4 channels except RST channel which only has 1 channel.
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A total of 17 channels. Following types are
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supported:
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0 - TX channel with 32bit transmit register and IRQ transmit
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acknowledgment support.
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1 - RX channel with 32bit receive register and IRQ support
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2 - TX doorbell channel. Without own register and no ACK support.
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3 - RX doorbell channel.
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4 - RST channel
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const: 2
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clocks:
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maxItems: 1
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fsl,mu-side-b:
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description: boolean, if present, means it is for side B MU.
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type: boolean
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- "#mbox-cells"
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx93-mu-s4
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then:
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properties:
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interrupt-names:
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minItems: 2
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interrupts:
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minItems: 2
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else:
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properties:
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interrupts:
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maxItems: 1
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not:
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required:
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- interrupt-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mailbox@5d1b0000 {
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compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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reg = <0x5d1b0000 0x10000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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};
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