e343d34a9c
Fix clock stop prepare timeout issue (#2853).
The trigger of internal circuit which belong to
“SDCA preset stuffs” was not set correctly in previous driver,
which could block clock_stop_preparation state.
Add the correct register setting to fix it.
Fixes: 20d17057f0 ('ASoC: rt715-sdca: Add RT715 sdca vendor-specific driver')
Signed-off-by: Jack Yu <jack.yu@realtek.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20210607222239.582139-12-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
138 lines
3.5 KiB
C
138 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* rt715-sdca.h -- RT715 ALSA SoC audio driver header
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*
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* Copyright(c) 2020 Realtek Semiconductor Corp.
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*/
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#ifndef __RT715_SDCA_H__
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#define __RT715_SDCA_H__
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#include <linux/regmap.h>
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#include <linux/soundwire/sdw.h>
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#include <linux/soundwire/sdw_type.h>
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#include <sound/soc.h>
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#include <linux/workqueue.h>
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#include <linux/device.h>
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struct rt715_sdca_priv {
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struct regmap *regmap;
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struct regmap *mbq_regmap;
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struct snd_soc_codec *codec;
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struct sdw_slave *slave;
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struct delayed_work adc_mute_work;
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int dbg_nid;
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int dbg_vid;
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int dbg_payload;
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enum sdw_slave_status status;
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struct sdw_bus_params params;
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bool hw_init;
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bool first_hw_init;
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int l_is_unmute;
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int r_is_unmute;
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int hw_sdw_ver;
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int kctl_switch_orig[4];
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int kctl_2ch_orig[2];
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int kctl_4ch_orig[4];
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int kctl_8ch_orig[8];
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};
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struct rt715_sdw_stream_data {
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struct sdw_stream_runtime *sdw_stream;
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};
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struct rt715_sdca_kcontrol_private {
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unsigned int reg_base;
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unsigned int count;
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unsigned int max;
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unsigned int shift;
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unsigned int invert;
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};
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/* MIPI Register */
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#define RT715_INT_CTRL 0x005a
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#define RT715_INT_MASK 0x005e
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/* NID */
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#define RT715_AUDIO_FUNCTION_GROUP 0x01
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#define RT715_MIC_ADC 0x07
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#define RT715_LINE_ADC 0x08
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#define RT715_MIX_ADC 0x09
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#define RT715_DMIC1 0x12
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#define RT715_DMIC2 0x13
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#define RT715_MIC1 0x18
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#define RT715_MIC2 0x19
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#define RT715_LINE1 0x1a
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#define RT715_LINE2 0x1b
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#define RT715_DMIC3 0x1d
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#define RT715_DMIC4 0x29
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#define RT715_VENDOR_REG 0x20
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#define RT715_MUX_IN1 0x22
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#define RT715_MUX_IN2 0x23
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#define RT715_MUX_IN3 0x24
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#define RT715_MUX_IN4 0x25
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#define RT715_MIX_ADC2 0x27
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#define RT715_INLINE_CMD 0x55
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#define RT715_VENDOR_HDA_CTL 0x61
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/* Index (NID:20h) */
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#define RT715_PRODUCT_NUM 0x0
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#define RT715_IRQ_CTRL 0x2b
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#define RT715_AD_FUNC_EN 0x36
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#define RT715_REV_1 0x37
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#define RT715_SDW_INPUT_SEL 0x39
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#define RT715_DFLL_VAD 0x44
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#define RT715_EXT_DMIC_CLK_CTRL2 0x54
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/* Index (NID:61h) */
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#define RT715_HDA_LEGACY_MUX_CTL1 0x00
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/* SDCA (Function) */
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#define FUN_JACK_CODEC 0x01
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#define FUN_MIC_ARRAY 0x02
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#define FUN_HID 0x03
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/* SDCA (Entity) */
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#define RT715_SDCA_ST_EN 0x00
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#define RT715_SDCA_CS_FREQ_IND_EN 0x01
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#define RT715_SDCA_FU_ADC8_9_VOL 0x02
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#define RT715_SDCA_SMPU_TRIG_ST_EN 0x05
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#define RT715_SDCA_FU_ADC10_11_VOL 0x06
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#define RT715_SDCA_FU_ADC7_27_VOL 0x0a
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#define RT715_SDCA_FU_AMIC_GAIN_EN 0x0c
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#define RT715_SDCA_FU_DMIC_GAIN_EN 0x0e
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#define RT715_SDCA_CX_CLK_SEL_EN 0x10
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#define RT715_SDCA_CREQ_POW_EN 0x18
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/* SDCA (Control) */
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#define RT715_SDCA_ST_CTRL 0x00
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#define RT715_SDCA_CX_CLK_SEL_CTRL 0x01
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#define RT715_SDCA_REQ_POW_CTRL 0x01
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#define RT715_SDCA_FU_MUTE_CTRL 0x01
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#define RT715_SDCA_FU_VOL_CTRL 0x02
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#define RT715_SDCA_FU_DMIC_GAIN_CTRL 0x0b
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#define RT715_SDCA_FREQ_IND_CTRL 0x10
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#define RT715_SDCA_SMPU_TRIG_EN_CTRL 0x10
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#define RT715_SDCA_SMPU_TRIG_ST_CTRL 0x11
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/* SDCA (Channel) */
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#define CH_00 0x00
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#define CH_01 0x01
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#define CH_02 0x02
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#define CH_03 0x03
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#define CH_04 0x04
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#define CH_05 0x05
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#define CH_06 0x06
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#define CH_07 0x07
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#define CH_08 0x08
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#define RT715_SDCA_DB_STEP 375
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enum {
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RT715_AIF1,
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RT715_AIF2,
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};
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int rt715_sdca_io_init(struct device *dev, struct sdw_slave *slave);
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int rt715_sdca_init(struct device *dev, struct regmap *mbq_regmap,
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struct regmap *regmap, struct sdw_slave *slave);
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#endif /* __RT715_SDCA_H__ */
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