cf719012b2
Some PLL clocks are N (multiplier) type clocks, or can be simplified as such. An example of the former is the DDR1 PLL clock on the A33. An example of the latter is the CPU PLL clock on the A80, in which the P divider is only used for low frequencies that are of little use. Both clocks support PLL lock detection. The mult clock macro implies support for this, but that is not true. The field is simply discarded. This patch adds proper support for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
171 lines
4.0 KiB
C
171 lines
4.0 KiB
C
/*
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* Copyright (C) 2016 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include "ccu_gate.h"
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#include "ccu_mult.h"
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struct _ccu_mult {
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unsigned long mult, min, max;
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};
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static void ccu_mult_find_best(unsigned long parent, unsigned long rate,
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struct _ccu_mult *mult)
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{
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int _mult;
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_mult = rate / parent;
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if (_mult < mult->min)
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_mult = mult->min;
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if (_mult > mult->max)
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_mult = mult->max;
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mult->mult = _mult;
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}
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static unsigned long ccu_mult_round_rate(struct ccu_mux_internal *mux,
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unsigned long parent_rate,
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unsigned long rate,
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void *data)
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{
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struct ccu_mult *cm = data;
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struct _ccu_mult _cm;
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_cm.min = cm->mult.min;
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if (cm->mult.max)
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_cm.max = cm->mult.max;
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else
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_cm.max = (1 << cm->mult.width) + cm->mult.offset - 1;
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ccu_mult_find_best(parent_rate, rate, &_cm);
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return parent_rate * _cm.mult;
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}
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static void ccu_mult_disable(struct clk_hw *hw)
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{
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struct ccu_mult *cm = hw_to_ccu_mult(hw);
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return ccu_gate_helper_disable(&cm->common, cm->enable);
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}
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static int ccu_mult_enable(struct clk_hw *hw)
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{
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struct ccu_mult *cm = hw_to_ccu_mult(hw);
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return ccu_gate_helper_enable(&cm->common, cm->enable);
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}
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static int ccu_mult_is_enabled(struct clk_hw *hw)
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{
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struct ccu_mult *cm = hw_to_ccu_mult(hw);
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return ccu_gate_helper_is_enabled(&cm->common, cm->enable);
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}
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static unsigned long ccu_mult_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ccu_mult *cm = hw_to_ccu_mult(hw);
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unsigned long val;
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u32 reg;
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if (ccu_frac_helper_is_enabled(&cm->common, &cm->frac))
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return ccu_frac_helper_read_rate(&cm->common, &cm->frac);
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reg = readl(cm->common.base + cm->common.reg);
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val = reg >> cm->mult.shift;
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val &= (1 << cm->mult.width) - 1;
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ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
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&parent_rate);
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return parent_rate * (val + cm->mult.offset);
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}
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static int ccu_mult_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct ccu_mult *cm = hw_to_ccu_mult(hw);
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return ccu_mux_helper_determine_rate(&cm->common, &cm->mux,
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req, ccu_mult_round_rate, cm);
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}
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static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_mult *cm = hw_to_ccu_mult(hw);
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struct _ccu_mult _cm;
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unsigned long flags;
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u32 reg;
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if (ccu_frac_helper_has_rate(&cm->common, &cm->frac, rate))
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return ccu_frac_helper_set_rate(&cm->common, &cm->frac, rate);
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else
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ccu_frac_helper_disable(&cm->common, &cm->frac);
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ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
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&parent_rate);
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_cm.min = cm->mult.min;
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if (cm->mult.max)
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_cm.max = cm->mult.max;
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else
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_cm.max = (1 << cm->mult.width) + cm->mult.offset - 1;
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ccu_mult_find_best(parent_rate, rate, &_cm);
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spin_lock_irqsave(cm->common.lock, flags);
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reg = readl(cm->common.base + cm->common.reg);
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reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift);
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reg |= ((_cm.mult - cm->mult.offset) << cm->mult.shift);
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writel(reg, cm->common.base + cm->common.reg);
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spin_unlock_irqrestore(cm->common.lock, flags);
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ccu_helper_wait_for_lock(&cm->common, cm->lock);
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return 0;
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}
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static u8 ccu_mult_get_parent(struct clk_hw *hw)
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{
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struct ccu_mult *cm = hw_to_ccu_mult(hw);
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return ccu_mux_helper_get_parent(&cm->common, &cm->mux);
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}
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static int ccu_mult_set_parent(struct clk_hw *hw, u8 index)
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{
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struct ccu_mult *cm = hw_to_ccu_mult(hw);
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return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index);
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}
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const struct clk_ops ccu_mult_ops = {
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.disable = ccu_mult_disable,
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.enable = ccu_mult_enable,
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.is_enabled = ccu_mult_is_enabled,
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.get_parent = ccu_mult_get_parent,
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.set_parent = ccu_mult_set_parent,
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.determine_rate = ccu_mult_determine_rate,
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.recalc_rate = ccu_mult_recalc_rate,
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.set_rate = ccu_mult_set_rate,
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};
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