f48f3ceabf
To reduce code duplicate and increase code readability use WDT core code to handle WDT interface. Remove io_lock as the WDT core uses mutex to lock each wdt device. Remove wdt_state as the WDT core tracks state with its own variable. The watchdog_init_timeout() can read timeout value from timeout-sec property if the passed value is out of bounds. The heartbeat is initialized in next way. If heartbeat is not set thought module parameter, try to read it's value from WDT node timeout-sec property. If node has no one, use default value. The heartbeat is hold in wdd->timeout by WDT core, so use it in order to set timeout period. Davinci WDT can't be stopped and once it's expired - it can be rearmed only after hardware reset, that's why nowayout feature is enforced. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
194 lines
4.9 KiB
C
194 lines
4.9 KiB
C
/*
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* drivers/char/watchdog/davinci_wdt.c
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*
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* Watchdog driver for DaVinci DM644x/DM646x processors
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*
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* Copyright (C) 2006-2013 Texas Instruments.
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/watchdog.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#define MODULE_NAME "DAVINCI-WDT: "
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#define DEFAULT_HEARTBEAT 60
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#define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
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/* Timer register set definition */
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#define PID12 (0x0)
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#define EMUMGT (0x4)
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#define TIM12 (0x10)
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#define TIM34 (0x14)
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#define PRD12 (0x18)
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#define PRD34 (0x1C)
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#define TCR (0x20)
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#define TGCR (0x24)
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#define WDTCR (0x28)
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/* TCR bit definitions */
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#define ENAMODE12_DISABLED (0 << 6)
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#define ENAMODE12_ONESHOT (1 << 6)
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#define ENAMODE12_PERIODIC (2 << 6)
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/* TGCR bit definitions */
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#define TIM12RS_UNRESET (1 << 0)
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#define TIM34RS_UNRESET (1 << 1)
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#define TIMMODE_64BIT_WDOG (2 << 2)
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/* WDTCR bit definitions */
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#define WDEN (1 << 14)
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#define WDFLAG (1 << 15)
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#define WDKEY_SEQ0 (0xa5c6 << 16)
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#define WDKEY_SEQ1 (0xda7e << 16)
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static int heartbeat;
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static void __iomem *wdt_base;
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struct clk *wdt_clk;
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static struct watchdog_device wdt_wdd;
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static int davinci_wdt_start(struct watchdog_device *wdd)
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{
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u32 tgcr;
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u32 timer_margin;
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unsigned long wdt_freq;
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wdt_freq = clk_get_rate(wdt_clk);
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/* disable, internal clock source */
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iowrite32(0, wdt_base + TCR);
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/* reset timer, set mode to 64-bit watchdog, and unreset */
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iowrite32(0, wdt_base + TGCR);
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tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
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iowrite32(tgcr, wdt_base + TGCR);
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/* clear counter regs */
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iowrite32(0, wdt_base + TIM12);
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iowrite32(0, wdt_base + TIM34);
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/* set timeout period */
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timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
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iowrite32(timer_margin, wdt_base + PRD12);
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timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
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iowrite32(timer_margin, wdt_base + PRD34);
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/* enable run continuously */
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iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
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/* Once the WDT is in pre-active state write to
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* TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
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* write protected (except for the WDKEY field)
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*/
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/* put watchdog in pre-active state */
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iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
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/* put watchdog in active state */
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iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
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return 0;
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}
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static int davinci_wdt_ping(struct watchdog_device *wdd)
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{
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/* put watchdog in service state */
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iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
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/* put watchdog in active state */
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iowrite32(WDKEY_SEQ1, wdt_base + WDTCR);
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return 0;
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}
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static const struct watchdog_info davinci_wdt_info = {
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.options = WDIOF_KEEPALIVEPING,
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.identity = "DaVinci Watchdog",
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};
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static const struct watchdog_ops davinci_wdt_ops = {
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.owner = THIS_MODULE,
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.start = davinci_wdt_start,
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.stop = davinci_wdt_ping,
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.ping = davinci_wdt_ping,
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};
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static int davinci_wdt_probe(struct platform_device *pdev)
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{
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int ret = 0;
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struct device *dev = &pdev->dev;
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struct resource *wdt_mem;
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struct watchdog_device *wdd;
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wdt_clk = devm_clk_get(dev, NULL);
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if (WARN_ON(IS_ERR(wdt_clk)))
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return PTR_ERR(wdt_clk);
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clk_prepare_enable(wdt_clk);
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wdd = &wdt_wdd;
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wdd->info = &davinci_wdt_info;
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wdd->ops = &davinci_wdt_ops;
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wdd->min_timeout = 1;
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wdd->max_timeout = MAX_HEARTBEAT;
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wdd->timeout = DEFAULT_HEARTBEAT;
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watchdog_init_timeout(wdd, heartbeat, dev);
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dev_info(dev, "heartbeat %d sec\n", wdd->timeout);
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watchdog_set_nowayout(wdd, 1);
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wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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wdt_base = devm_ioremap_resource(dev, wdt_mem);
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if (IS_ERR(wdt_base))
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return PTR_ERR(wdt_base);
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ret = watchdog_register_device(wdd);
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if (ret < 0)
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dev_err(dev, "cannot register watchdog device\n");
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return ret;
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}
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static int davinci_wdt_remove(struct platform_device *pdev)
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{
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watchdog_unregister_device(&wdt_wdd);
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clk_disable_unprepare(wdt_clk);
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return 0;
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}
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static const struct of_device_id davinci_wdt_of_match[] = {
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{ .compatible = "ti,davinci-wdt", },
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{},
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};
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MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
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static struct platform_driver platform_wdt_driver = {
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.driver = {
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.name = "davinci-wdt",
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.owner = THIS_MODULE,
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.of_match_table = davinci_wdt_of_match,
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},
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.probe = davinci_wdt_probe,
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.remove = davinci_wdt_remove,
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};
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module_platform_driver(platform_wdt_driver);
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MODULE_AUTHOR("Texas Instruments");
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MODULE_DESCRIPTION("DaVinci Watchdog Driver");
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat,
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"Watchdog heartbeat period in seconds from 1 to "
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__MODULE_STRING(MAX_HEARTBEAT) ", default "
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__MODULE_STRING(DEFAULT_HEARTBEAT));
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:davinci-wdt");
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