Peter Zijlstra f4b4b45652 perf/x86: Fix out of bound MSR access ... On Wed, Jul 28, 2021 at 12:49:43PM -0400, Vince Weaver wrote: > [32694.087403] unchecked MSR access error: WRMSR to 0x318 (tried to write 0x0000000000000000) at rIP: 0xffffffff8106f854 (native_write_msr+0x4/0x20) > [32694.101374] Call Trace: > [32694.103974] perf_clear_dirty_counters+0x86/0x100 The problem being that it doesn't filter out all fake counters, in specific the above (erroneously) tries to use FIXED_BTS. Limit the fixed counters indexes to the hardware supplied number. Reported-by: Vince Weaver <vincent.weaver@maine.edu> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Vince Weaver <vincent.weaver@maine.edu> Tested-by: Like Xu <likexu@tencent.com> Link: https://lkml.kernel.org/r/YQJxka3dxgdIdebG@hirez.programming.kicks-ass.net		2021-08-04 15:16:33 +02:00
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amd	Handle power-gating of AMD IOMMU perf counters properly when they are used.	2021-05-09 13:00:26 -07:00
intel	A fix and a hardware-enablement addition:	2021-07-11 11:10:48 -07:00
zhaoxin	x86: Fix various typos in comments	2021-03-18 15:31:53 +01:00
core.c	perf/x86: Fix out of bound MSR access	2021-08-04 15:16:33 +02:00
Kconfig	treewide: replace '---help---' in Kconfig files with 'help'	2020-06-14 01:57:21 +09:00
Makefile	perf/x86/rapl: Fix RAPL config variable bug	2020-06-02 11:52:56 +02:00
msr.c	perf/x86/msr: Add Alder Lake CPU support	2021-04-19 20:03:29 +02:00
perf_event.h	Perf events updates for this cycle:	2021-06-28 12:03:20 -07:00
probe.c	perf/x86/rapl: Add msr mask support	2021-02-10 14:44:54 +01:00
probe.h	perf/x86/rapl: Add msr mask support	2021-02-10 14:44:54 +01:00
rapl.c	perf/x86/rapl: Use CPUID bit on AMD and Hygon parts	2021-06-01 21:10:33 +02:00