Sowjanya Komatineni f4ce428c41
spi: tegra114: configure dma burst size to fifo trig level
Fixes: Configure DMA burst size to be same as SPI TX/RX trigger levels
to avoid mismatch.

SPI FIFO trigger levels are calculated based on the transfer length.
So this patch moves DMA slave configuration to happen before start
of DMAs.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-01 15:39:42 +07:00
..
2018-11-05 11:55:06 +00:00
2017-08-10 15:50:23 +01:00
2017-05-26 12:41:07 +01:00
2019-03-11 16:40:00 +00:00