Florian Fainelli f5337346cd arm64: pmu: Wire-up Cortex A53 L2 cache events and DTLB refills
Add missing L2 cache events: read/write accesses and misses, as well as
the DTLB refills.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-28 15:23:36 +01:00
..
2017-02-14 15:13:43 -05:00
2017-04-04 17:03:32 +01:00