3ac7165d72
Convert the bindings of the Freescale Pixel Pipeline to YAML. The conversion drops the previously listed compatibles for several SoCs. It is unclear, if the PXP on these SoCs is compatible to any of the PXPs on the existing SoCs and would allow to reuse the already defined compatibles. The missing compatibles should be brought back when the support for the PXP on these SoCs is added. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
89 lines
1.8 KiB
YAML
89 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/fsl,imx6ull-pxp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Pixel Pipeline
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maintainers:
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- Philipp Zabel <p.zabel@pengutronix.de>
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- Michael Tretter <m.tretter@pengutronix.de>
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description:
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The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
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that supports scaling, colorspace conversion, alpha blending, rotation, and
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pixel conversion via lookup table. Different versions are present on various
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i.MX SoCs from i.MX23 to i.MX7.
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,imx6ul-pxp
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- fsl,imx6ull-pxp
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- fsl,imx7d-pxp
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- items:
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- enum:
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- fsl,imx6sll-pxp
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- fsl,imx6sx-pxp
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- const: fsl,imx6ull-pxp
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 2
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clocks:
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maxItems: 1
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clock-names:
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const: axi
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6sx-pxp
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- fsl,imx6ul-pxp
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then:
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properties:
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interrupts:
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maxItems: 1
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else:
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properties:
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interrupts:
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minItems: 2
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maxItems: 2
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx6ul-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pxp: pxp@21cc000 {
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compatible = "fsl,imx6ull-pxp";
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reg = <0x021cc000 0x4000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "axi";
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clocks = <&clks IMX6UL_CLK_PXP>;
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};
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