716f974896
The i.MX8MP ISP is compatbile with the rkisp1 driver. Add it to the list of compatible strings. While at it, expand on the description of the clocks to make it clear which clock in the i.MX8MP ISP they map to, based on the names from the datasheet. Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Tested-by: Adam Ford <aford173@gmail.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
321 lines
7.7 KiB
YAML
321 lines
7.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip SoC Image Signal Processing unit v1
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maintainers:
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- Helen Koike <helen.koike@collabora.com>
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description: |
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Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
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which contains image processing, scaling, and compression functions.
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properties:
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compatible:
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enum:
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- fsl,imx8mp-isp
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- rockchip,px30-cif-isp
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- rockchip,rk3399-cif-isp
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 3
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interrupt-names:
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items:
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- const: isp
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- const: mi
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- const: mipi
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clocks:
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minItems: 3
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items:
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# isp0 and isp1
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- description: ISP clock (for imx8mp, clk)
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- description: ISP AXI clock (for imx8mp, m_hclk)
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- description: ISP AHB clock (for imx8mp, hclk)
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# only for isp1
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- description: ISP Pixel clock
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clock-names:
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minItems: 3
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items:
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# isp0 and isp1
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- const: isp
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- const: aclk
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- const: hclk
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# only for isp1
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- const: pclk
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fsl,blk-ctrl:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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description:
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A phandle to the media block control for the ISP, followed by a cell
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containing the index of the gasket.
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iommus:
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maxItems: 1
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phys:
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maxItems: 1
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description: phandle for the PHY port
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phy-names:
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const: dphy
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power-domains:
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description: connection point for sensors at MIPI-DPHY RX0
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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maxItems: 4
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port@1:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description: connection point for input on the parallel interface
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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bus-type:
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enum: [5, 6]
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required:
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- bus-type
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anyOf:
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- required:
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- port@0
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- required:
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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- ports
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: rockchip,rk3399-cif-isp
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 4
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clock-names:
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minItems: 3
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maxItems: 4
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- if:
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properties:
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compatible:
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contains:
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const: rockchip,px30-cif-isp
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then:
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required:
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- interrupt-names
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx8mp-isp
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then:
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properties:
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iommus: false
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phys: false
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phy-names: false
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required:
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- fsl,blk-ctrl
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else:
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properties:
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fsl,blk-ctrl: false
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required:
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- iommus
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- phys
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- phy-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rk3399-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/rk3399-power.h>
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parent0: parent {
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#address-cells = <2>;
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#size-cells = <2>;
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isp0: isp0@ff910000 {
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compatible = "rockchip,rk3399-cif-isp";
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reg = <0x0 0xff910000 0x0 0x4000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru SCLK_ISP0>,
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<&cru ACLK_ISP0_WRAPPER>,
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<&cru HCLK_ISP0_WRAPPER>;
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clock-names = "isp", "aclk", "hclk";
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iommus = <&isp0_mmu>;
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phys = <&dphy>;
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phy-names = "dphy";
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power-domains = <&power RK3399_PD_ISP0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_wcam: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&wcam_out>;
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data-lanes = <1 2>;
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};
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mipi_in_ucam: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ucam_out>;
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data-lanes = <1>;
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};
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};
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};
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};
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i2c7: i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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wcam: camera@36 {
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compatible = "ovti,ov5695";
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reg = <0x36>;
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clocks = <&cru SCLK_TESTCLKOUT1>;
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port {
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wcam_out: endpoint {
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remote-endpoint = <&mipi_in_wcam>;
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data-lanes = <1 2>;
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};
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};
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};
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ucam: camera@3c {
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compatible = "ovti,ov2685";
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reg = <0x3c>;
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clocks = <&cru SCLK_TESTCLKOUT1>;
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clock-names = "xvclk";
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avdd-supply = <&pp2800_cam>;
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dovdd-supply = <&pp1800>;
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dvdd-supply = <&pp1800>;
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port {
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ucam_out: endpoint {
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remote-endpoint = <&mipi_in_ucam>;
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data-lanes = <1>;
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};
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};
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};
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};
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/px30-power.h>
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parent1: parent {
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#address-cells = <2>;
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#size-cells = <2>;
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isp: isp@ff4a0000 {
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compatible = "rockchip,px30-cif-isp";
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reg = <0x0 0xff4a0000 0x0 0x8000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "isp", "mi", "mipi";
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clocks = <&cru SCLK_ISP0>,
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<&cru ACLK_ISP0_WRAPPER>,
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<&cru HCLK_ISP0_WRAPPER>,
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<&cru PCLK_ISP1_WRAPPER>;
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clock-names = "isp", "aclk", "hclk", "pclk";
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iommus = <&isp_mmu>;
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phys = <&csi_dphy>;
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phy-names = "dphy";
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power-domains = <&power PX30_PD_VI>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_ucam1: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ucam1_out>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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i2c2: i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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ov5695: camera@36 {
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compatible = "ovti,ov5647";
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reg = <0x36>;
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clocks = <&cru SCLK_CIF_OUT>;
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port {
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ucam1_out: endpoint {
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remote-endpoint = <&mipi_in_ucam1>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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};
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