As far as I can tell the only reason microblaze has __ARCH_WANT_INTERRUPTS_ON_CTXSW is because it initializes new task state with interrupts enabled so that on switch_to() interrupts get enabled. So change copy_thread() to clear MSR_IE instead of set it, this will ensure switch_to() will always keep IRQs disabled. The scheduler will disable IRQs when taking rq->lock in schedule() and enable IRQs in finish_lock_switch() after its done its magic. This leaves ARM the only __ARCH_WANT_INTERRUPTS_ON_CTXSW user. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by: Michal Simek <monstr@monstr.eu>
		
			
				
	
	
		
			259 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			259 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
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|  * Copyright (C) 2008-2009 PetaLogix
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|  * Copyright (C) 2006 Atmark Techno, Inc.
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|  *
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|  * This file is subject to the terms and conditions of the GNU General Public
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|  * License. See the file "COPYING" in the main directory of this archive
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|  * for more details.
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|  */
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| 
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| #include <linux/module.h>
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| #include <linux/sched.h>
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| #include <linux/pm.h>
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| #include <linux/tick.h>
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| #include <linux/bitops.h>
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| #include <asm/system.h>
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| #include <asm/pgalloc.h>
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| #include <asm/uaccess.h> /* for USER_DS macros */
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| #include <asm/cacheflush.h>
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| 
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| void show_regs(struct pt_regs *regs)
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| {
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| 	printk(KERN_INFO " Registers dump: mode=%X\r\n", regs->pt_mode);
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| 	printk(KERN_INFO " r1=%08lX, r2=%08lX, r3=%08lX, r4=%08lX\n",
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| 				regs->r1, regs->r2, regs->r3, regs->r4);
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| 	printk(KERN_INFO " r5=%08lX, r6=%08lX, r7=%08lX, r8=%08lX\n",
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| 				regs->r5, regs->r6, regs->r7, regs->r8);
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| 	printk(KERN_INFO " r9=%08lX, r10=%08lX, r11=%08lX, r12=%08lX\n",
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| 				regs->r9, regs->r10, regs->r11, regs->r12);
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| 	printk(KERN_INFO " r13=%08lX, r14=%08lX, r15=%08lX, r16=%08lX\n",
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| 				regs->r13, regs->r14, regs->r15, regs->r16);
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| 	printk(KERN_INFO " r17=%08lX, r18=%08lX, r19=%08lX, r20=%08lX\n",
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| 				regs->r17, regs->r18, regs->r19, regs->r20);
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| 	printk(KERN_INFO " r21=%08lX, r22=%08lX, r23=%08lX, r24=%08lX\n",
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| 				regs->r21, regs->r22, regs->r23, regs->r24);
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| 	printk(KERN_INFO " r25=%08lX, r26=%08lX, r27=%08lX, r28=%08lX\n",
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| 				regs->r25, regs->r26, regs->r27, regs->r28);
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| 	printk(KERN_INFO " r29=%08lX, r30=%08lX, r31=%08lX, rPC=%08lX\n",
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| 				regs->r29, regs->r30, regs->r31, regs->pc);
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| 	printk(KERN_INFO " msr=%08lX, ear=%08lX, esr=%08lX, fsr=%08lX\n",
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| 				regs->msr, regs->ear, regs->esr, regs->fsr);
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| }
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| 
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| void (*pm_idle)(void);
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| void (*pm_power_off)(void) = NULL;
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| EXPORT_SYMBOL(pm_power_off);
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| 
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| static int hlt_counter = 1;
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| 
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| void disable_hlt(void)
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| {
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| 	hlt_counter++;
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| }
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| EXPORT_SYMBOL(disable_hlt);
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| 
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| void enable_hlt(void)
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| {
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| 	hlt_counter--;
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| }
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| EXPORT_SYMBOL(enable_hlt);
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| 
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| static int __init nohlt_setup(char *__unused)
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| {
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| 	hlt_counter = 1;
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| 	return 1;
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| }
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| __setup("nohlt", nohlt_setup);
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| 
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| static int __init hlt_setup(char *__unused)
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| {
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| 	hlt_counter = 0;
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| 	return 1;
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| }
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| __setup("hlt", hlt_setup);
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| 
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| void default_idle(void)
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| {
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| 	if (likely(hlt_counter)) {
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| 		local_irq_disable();
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| 		stop_critical_timings();
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| 		cpu_relax();
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| 		start_critical_timings();
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| 		local_irq_enable();
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| 	} else {
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| 		clear_thread_flag(TIF_POLLING_NRFLAG);
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| 		smp_mb__after_clear_bit();
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| 		local_irq_disable();
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| 		while (!need_resched())
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| 			cpu_sleep();
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| 		local_irq_enable();
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| 		set_thread_flag(TIF_POLLING_NRFLAG);
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| 	}
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| }
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| 
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| void cpu_idle(void)
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| {
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| 	set_thread_flag(TIF_POLLING_NRFLAG);
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| 
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| 	/* endless idle loop with no priority at all */
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| 	while (1) {
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| 		void (*idle)(void) = pm_idle;
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| 
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| 		if (!idle)
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| 			idle = default_idle;
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| 
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| 		tick_nohz_stop_sched_tick(1);
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| 		while (!need_resched())
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| 			idle();
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| 		tick_nohz_restart_sched_tick();
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| 
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| 		preempt_enable_no_resched();
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| 		schedule();
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| 		preempt_disable();
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| 		check_pgt_cache();
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| 	}
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| }
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| 
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| void flush_thread(void)
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| {
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| }
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| 
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| int copy_thread(unsigned long clone_flags, unsigned long usp,
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| 		unsigned long unused,
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| 		struct task_struct *p, struct pt_regs *regs)
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| {
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| 	struct pt_regs *childregs = task_pt_regs(p);
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| 	struct thread_info *ti = task_thread_info(p);
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| 
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| 	*childregs = *regs;
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| 	if (user_mode(regs))
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| 		childregs->r1 = usp;
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| 	else
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| 		childregs->r1 = ((unsigned long) ti) + THREAD_SIZE;
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| 
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| #ifndef CONFIG_MMU
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| 	memset(&ti->cpu_context, 0, sizeof(struct cpu_context));
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| 	ti->cpu_context.r1 = (unsigned long)childregs;
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| 	ti->cpu_context.msr = (unsigned long)childregs->msr;
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| #else
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| 
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| 	/* if creating a kernel thread then update the current reg (we don't
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| 	 * want to use the parent's value when restoring by POP_STATE) */
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| 	if (kernel_mode(regs))
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| 		/* save new current on stack to use POP_STATE */
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| 		childregs->CURRENT_TASK = (unsigned long)p;
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| 	/* if returning to user then use the parent's value of this register */
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| 
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| 	/* if we're creating a new kernel thread then just zeroing all
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| 	 * the registers. That's OK for a brand new thread.*/
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| 	/* Pls. note that some of them will be restored in POP_STATE */
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| 	if (kernel_mode(regs))
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| 		memset(&ti->cpu_context, 0, sizeof(struct cpu_context));
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| 	/* if this thread is created for fork/vfork/clone, then we want to
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| 	 * restore all the parent's context */
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| 	/* in addition to the registers which will be restored by POP_STATE */
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| 	else {
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| 		ti->cpu_context = *(struct cpu_context *)regs;
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| 		childregs->msr |= MSR_UMS;
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| 	}
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| 
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| 	/* FIXME STATE_SAVE_PT_OFFSET; */
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| 	ti->cpu_context.r1  = (unsigned long)childregs;
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| 	/* we should consider the fact that childregs is a copy of the parent
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| 	 * regs which were saved immediately after entering the kernel state
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| 	 * before enabling VM. This MSR will be restored in switch_to and
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| 	 * RETURN() and we want to have the right machine state there
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| 	 * specifically this state must have INTs disabled before and enabled
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| 	 * after performing rtbd
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| 	 * compose the right MSR for RETURN(). It will work for switch_to also
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| 	 * excepting for VM and UMS
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| 	 * don't touch UMS , CARRY and cache bits
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| 	 * right now MSR is a copy of parent one */
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| 	childregs->msr |= MSR_BIP;
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| 	childregs->msr &= ~MSR_EIP;
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| 	childregs->msr |= MSR_IE;
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| 	childregs->msr &= ~MSR_VM;
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| 	childregs->msr |= MSR_VMS;
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| 	childregs->msr |= MSR_EE; /* exceptions will be enabled*/
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| 
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| 	ti->cpu_context.msr = (childregs->msr|MSR_VM);
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| 	ti->cpu_context.msr &= ~MSR_UMS; /* switch_to to kernel mode */
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| 	ti->cpu_context.msr &= ~MSR_IE;
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| #endif
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| 	ti->cpu_context.r15 = (unsigned long)ret_from_fork - 8;
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| 
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| 	if (clone_flags & CLONE_SETTLS)
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| 		;
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| 
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| 	return 0;
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| }
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| 
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| #ifndef CONFIG_MMU
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| /*
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|  * Return saved PC of a blocked thread.
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|  */
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| unsigned long thread_saved_pc(struct task_struct *tsk)
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| {
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| 	struct cpu_context *ctx =
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| 		&(((struct thread_info *)(tsk->stack))->cpu_context);
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| 
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| 	/* Check whether the thread is blocked in resume() */
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| 	if (in_sched_functions(ctx->r15))
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| 		return (unsigned long)ctx->r15;
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| 	else
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| 		return ctx->r14;
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| }
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| #endif
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| 
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| static void kernel_thread_helper(int (*fn)(void *), void *arg)
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| {
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| 	fn(arg);
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| 	do_exit(-1);
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| }
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| 
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| int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
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| {
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| 	struct pt_regs regs;
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| 
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| 	memset(®s, 0, sizeof(regs));
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| 	/* store them in non-volatile registers */
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| 	regs.r5 = (unsigned long)fn;
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| 	regs.r6 = (unsigned long)arg;
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| 	local_save_flags(regs.msr);
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| 	regs.pc = (unsigned long)kernel_thread_helper;
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| 	regs.pt_mode = 1;
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| 
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| 	return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0,
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| 			®s, 0, NULL, NULL);
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| }
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| EXPORT_SYMBOL_GPL(kernel_thread);
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| 
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| unsigned long get_wchan(struct task_struct *p)
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| {
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| /* TBD (used by procfs) */
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| 	return 0;
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| }
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| 
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| /* Set up a thread for executing a new program */
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| void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long usp)
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| {
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| 	regs->pc = pc;
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| 	regs->r1 = usp;
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| 	regs->pt_mode = 0;
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| #ifdef CONFIG_MMU
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| 	regs->msr |= MSR_UMS;
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| #endif
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| }
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| 
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| #ifdef CONFIG_MMU
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| #include <linux/elfcore.h>
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| /*
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|  * Set up a thread for executing a new program
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|  */
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| int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpregs)
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| {
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| 	return 0; /* MicroBlaze has no separate FPU registers */
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| }
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| #endif /* CONFIG_MMU */
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