Eugeniy Paltsev f6a09bace0 ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk ...

Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

2017-09-01 11:26:25 -07:00

..

boot

ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk

2017-09-01 11:26:25 -07:00

configs

ARC: [plat-sim] Include this platform unconditionally

2017-08-04 13:49:47 +05:30

include

ARCv2: SLC: provide a line based flush routine for debugging

2017-08-30 09:21:34 -07:00

kernel

ARC: [plat-eznps] handle extra aux regs #2: kernel/entry exit

2017-08-28 15:17:36 -07:00

lib

ARC: dw2 unwind: enable cfi pseudo ops in string lib

2016-09-30 14:48:22 -07:00

mm

ARCv2: SLC: provide a line based flush routine for debugging

2017-08-30 09:21:34 -07:00

oprofile

ARC: OProfile support

2013-02-15 23:16:00 +05:30

plat-axs10x

ARC: [plat-axs103] use clk driver #1: Get rid of platform specific cpu clk setting

2017-09-01 11:26:24 -07:00

plat-eznps

ARC: [plat-eznps] handle extra aux regs #1: save/restore on context switch

2017-08-28 15:17:36 -07:00

plat-sim

ARC: [plat-sim] Include this platform unconditionally

2017-08-04 13:49:47 +05:30

plat-tb10x

arc: select GPIOLIB directly

2016-04-26 14:07:59 +02:00

Kbuild

…

Kconfig

ARC: [plat-sim] Include this platform unconditionally

2017-08-04 13:49:47 +05:30

Kconfig.debug

ARC: With earlycon in use, retire EARLY_PRINTK

2015-05-11 11:20:21 +05:30

Makefile

ARC: [plat-sim] Include this platform unconditionally

2017-08-04 13:49:47 +05:30