1bf8cc3d01
OPPs can be populated statically, via DT, or added at run time with dev_pm_opp_add(). While this driver handles the first case correctly, it would fail to populate OPPs added at runtime. Because call to of_init_opp_table() would fail as there are no OPPs in DT and probe will return early. To fix this, remove error checking and call dev_pm_opp_init_cpufreq_table() unconditionally. Update bindings as well. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
65 lines
1.5 KiB
Plaintext
65 lines
1.5 KiB
Plaintext
Generic CPU0 cpufreq driver
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It is a generic cpufreq driver for CPU0 frequency management. It
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supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
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systems which share clock and voltage across all CPUs.
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Both required and optional properties listed below must be defined
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under node /cpus/cpu@0.
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Required properties:
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- None
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Optional properties:
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- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt for
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details. OPPs *must* be supplied either via DT, i.e. this property, or
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populated at runtime.
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- clock-latency: Specify the possible maximum transition latency for clock,
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in unit of nanoseconds.
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- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
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- #cooling-cells:
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- cooling-min-level:
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- cooling-max-level:
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Please refer to Documentation/devicetree/bindings/thermal/thermal.txt.
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Examples:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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792000 1100000
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396000 950000
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198000 850000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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cooling-max-level = <2>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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cpu@2 {
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compatible = "arm,cortex-a9";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a9";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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