9952f6918d
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
100 lines
2.5 KiB
C
100 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/bug.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <soc/tegra/fuse.h>
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#include "fuse.h"
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#define CPU_SPEEDO_LSBIT 20
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#define CPU_SPEEDO_MSBIT 29
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#define CPU_SPEEDO_REDUND_LSBIT 30
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#define CPU_SPEEDO_REDUND_MSBIT 39
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#define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
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#define SOC_SPEEDO_LSBIT 40
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#define SOC_SPEEDO_MSBIT 47
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#define SOC_SPEEDO_REDUND_LSBIT 48
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#define SOC_SPEEDO_REDUND_MSBIT 55
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#define SOC_SPEEDO_REDUND_OFFS (SOC_SPEEDO_REDUND_MSBIT - SOC_SPEEDO_MSBIT)
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#define SPEEDO_MULT 4
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#define PROCESS_CORNERS_NUM 4
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#define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2)
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#define SPEEDO_ID_SELECT_1(sku) \
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(((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
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((sku) != 27) && ((sku) != 28))
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enum {
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SPEEDO_ID_0,
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SPEEDO_ID_1,
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SPEEDO_ID_2,
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SPEEDO_ID_COUNT,
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};
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static const u32 __initconst cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
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{315, 366, 420, UINT_MAX},
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{303, 368, 419, UINT_MAX},
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{316, 331, 383, UINT_MAX},
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};
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static const u32 __initconst soc_process_speedos[][PROCESS_CORNERS_NUM] = {
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{165, 195, 224, UINT_MAX},
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{165, 195, 224, UINT_MAX},
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{165, 195, 224, UINT_MAX},
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};
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void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
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{
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u32 reg;
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u32 val;
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int i;
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BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
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BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) != SPEEDO_ID_COUNT);
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if (SPEEDO_ID_SELECT_0(sku_info->revision))
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sku_info->soc_speedo_id = SPEEDO_ID_0;
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else if (SPEEDO_ID_SELECT_1(sku_info->sku_id))
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sku_info->soc_speedo_id = SPEEDO_ID_1;
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else
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sku_info->soc_speedo_id = SPEEDO_ID_2;
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val = 0;
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for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
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reg = tegra_fuse_read_spare(i) |
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tegra_fuse_read_spare(i + CPU_SPEEDO_REDUND_OFFS);
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val = (val << 1) | (reg & 0x1);
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}
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val = val * SPEEDO_MULT;
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pr_debug("Tegra CPU speedo value %u\n", val);
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for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
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if (val <= cpu_process_speedos[sku_info->soc_speedo_id][i])
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break;
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}
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sku_info->cpu_process_id = i;
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val = 0;
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for (i = SOC_SPEEDO_MSBIT; i >= SOC_SPEEDO_LSBIT; i--) {
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reg = tegra_fuse_read_spare(i) |
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tegra_fuse_read_spare(i + SOC_SPEEDO_REDUND_OFFS);
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val = (val << 1) | (reg & 0x1);
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}
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val = val * SPEEDO_MULT;
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pr_debug("Core speedo value %u\n", val);
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for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
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if (val <= soc_process_speedos[sku_info->soc_speedo_id][i])
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break;
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}
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sku_info->soc_process_id = i;
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}
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