Sean Paul f892f24b37 clk: tegra124: Add init data for dsi lp clocks
Set the parent of the dsi lp clocks to pll_p and the rate
to 68MHz. The default parent is clk_m and rate is 12MHz, this
is too slow to receive data from the peripheral.

Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz
will suffice.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2015-02-02 15:46:34 +02:00
..